/* config.h - Kontron MSMST BSP configuration header */

/*
 * Copyright (c) 2010 Wind River Systems, Inc.
 *
 * The right to copy, distribute, modify or otherwise make use
 * of this software may be licensed only pursuant to the terms
 * of an applicable Wind River license agreement.
 */

/* Copyright 2010-2011 Kontron (KGSC) */

/*
modification history
--------------------
01d,22jun11,ivo  update for MSMST
01c,08feb11,edv  remove unused drivers, USB PC console workarounds 
01b,10nov10,kpn  Adjusted to Kontron etx-tt board
01a,10apr10,rbc  created based on itl_crownbeach/config.h (01g)
*/

/*
DESCRIPTION
This module contains the configuration parameters for the
Kontron MSMST board.
*/

#ifndef __INCconfigh
#define __INCconfigh

#ifdef __cplusplus
extern "C" {
#endif

/* BSP version/revision identification, before configAll.h */

#define BSP_VERSION "R01"   /* vxWorks 6.x BSP */
#define BSP_REV     ".00"    /* increment by whole numbers */

#include <vsbConfig.h>
#include <configAll.h>
#include <MSMST.h>

/* BSP specific prototypes that must be in config.h */

#ifndef _ASMLANGUAGE
    IMPORT void sysHwInit0 (void);
    IMPORT UINT8 *sysInumTbl;      /* IRQ vs intNum table */
#endif /* !_ASMLANGUAGE */

/*
 * MP Table boot options (select only one)
 * Definitions below apply only to bootApp images.
 * Other images use an MP table left behind in memory by the bootApp
 */
#undef INCLUDE_ACPI_BOOT_OP     /* define if bootrom uses ACPI for MP table */
#undef INCLUDE_USR_BOOT_OP      /* user defined MP table */
#if ((!defined INCLUDE_ACPI_BOOT_OP) && (!defined INCLUDE_USR_BOOT_OP))
#define  INCLUDE_MPTABLE_BOOT_OP /* bios provides MP table (default) */
#endif

#define INCLUDE_USR_MPAPIC      /* MPAPIC table initialzation */

#if (defined INCLUDE_ACPI_BOOT_OP) && (defined BOOTAPP) && \
    (!defined INCLUDE_BOOT_RAM_IMAGE)
#define INCLUDE_ACPI_MPAPIC  /* ACPI loads MP apic table */
#endif

/* define this to view ACPI log and error messages during the boot sequence */
#undef INCLUDE_ACPI_DEBUG_PRINT


/* define this to enable early formatted print statments. */
#undef INCLUDE_EARLY_PRINT


/* BSP specific initialization (before cacheLibInit() is called) */

#define INCLUDE_SYS_HW_INIT_0
#define SYS_HW_INIT_0()         (sysHwInit0())

/* CPU auto detection with sysCpuProbe() that support Intel CPUs for now */

#define  INCLUDE_CPU_PROBE         /* define to perform sysCpuProbe() */
#   undef  CPU
#   define CPU      PENTIUM4     /* for CPU conditionals in BSP */
#define X86CPU_DEFAULT  X86CPU_PENTIUM4  /* for sysProcessor set in BSP */

/* SYS_MODEL defines */

#ifdef _WRS_CONFIG_SMP
/* STRICTLY SMP BASED BSP, one must be built with _WRS_CONFIG_SMP defined!!! */

#define SYS_MODEL "Kontron MSMST SMP"

#   define INCLUDE_VXIPI

/* SMP AP specific defines... */

/*
 * NOTE: if sysInitCpuStartup changes the value of CPU_STARTUP_SIZE
 *       will need to be recalculated...
 */

#   define CPU_STARTUP_SIZE    0x00A8  /* size of sysInitCpuStartup */

#   define CPU_ENTRY_POINT     0xC000  /* cold start code location for APs */
#   define CPU_SCRATCH_START   0x0100  /* start of scratch memory */
#   define CPU_AP_AREA         0x200   /* work area for APs */

    /* offset for scratch memory */

#   define CPU_SCRATCH_POINT   (CPU_ENTRY_POINT + CPU_SCRATCH_START)

#   define NUM_GDT_ENTRIES     0x0A

#   define CPU_SCRATCH_GDT     0x2E
#   define CPU_SCRATCH_IDT     0x3A

#   define LIM_GDT_OFFSET      0x2C
#   define BASE_GDT_OFFSET     0x30
#   define CR3_OFFSET          0x34
#   define LIM_IDT_OFFSET      0x38
#   define BASE_IDT_OFFSET     0x3C
#   define AP_STK_OFFSET       0x40

#else  /* _WRS_CONFIG_SMP */
#define SYS_MODEL "Kontron MSMST"
#endif /* _WRS_CONFIG_SMP */

/* Default boot line */
    
#define DEFAULT_BOOT_LINE_NET \
    "gei(0,0)host:vxWorks h=10.0.0.1 e=10.0.0.6:0xffffff00 f=0x2 u=target pw=qq"

    /* boot from usb mass storage device */
#define DEFAULT_BOOT_LINE_USB \
        "usb(0,0)host:/bd0/vxWorks h=192.168.100.1 e=192.168.100.10:0xffffff00 u=target"

    /* boot from SATA disk */
#define DEFAULT_BOOT_LINE_SATA \
    "ata=0,1(0,0)host:/s0p1:2/vxWorks h=10.0.0.1 e=10.0.0.6:0xffffff0 f=0x2 o=gei0"

#define DEFAULT_BOOT_LINE DEFAULT_BOOT_LINE_NET

/* 
 * boot devices 
 */
#undef INCLUDE_DRV_STORAGE_INTEL_AHCI /* include AHCI SATA disk driver */
#define DRV_STORAGE_SI31XX /* include  SATA disk driver */
#undef INCLUDE_USB /* USB boot devices */
#undef INCLUDE_PC_CONSOLE  /* USB keyboard and VGA console:
			NOTE: you should also enable INCLUDE_USB to properly activate 
			USB keyboard when USB leagacy support is disabled in BIOS
			(see also the BSP release notes) */

/* when INCLUDE_PC_CONSOLE is disabled 
 * the serial port COM1 is used 
 * with specified baud rate */    
#undef CONSOLE_BAUD_RATE
#define CONSOLE_BAUD_RATE       115200    /* console baud rate */
    
/* Warm boot (reboot) devices and parameters */

#define SYS_WARM_BIOS       0   /* warm start from BIOS */
#define SYS_WARM_FD         1   /* warm start from FD */
#define SYS_WARM_ATA        2   /* warm start from ATA */
#define SYS_WARM_TFFS       3   /* warm start from Flash */
#define SYS_WARM_USB        4   /* warm start from USB */
#define SYS_WARM_ICH        5   /* warm start from ICH(IDE) */
#define SYS_WARM_AHCI       6   /* warm start from AHCI */

#define SYS_WARM_TYPE       SYS_WARM_BIOS /* warm start device */
#define SYS_WARM_FD_DRIVE       0         /* 0 = drive a:, 1 = b: */
#define SYS_WARM_FD_TYPE        0         /* 0 = 3.5" 2HD, 1 = 5.25" 2HD */
#define SYS_WARM_ATA_CTRL       0         /* controller 0 */
#define SYS_WARM_ATA_DRIVE      0         /* 0 = c:, 1 = d: */
#define SYS_WARM_TFFS_DRIVE     0       /* 0 = c: */
#define SYS_WARM_USB_DRIVE      0       /* 0 */
#define SYS_WARM_ICH_CTRL       0       /* controller 0 */
#define SYS_WARM_ICH_DRIVE      0       /* 0 = c:, 1 = d: */
#define SYS_WARM_AHCI_CTRL      0       /* controller 0 */
#define SYS_WARM_AHCI_DRIVE     0       /* 0 = c:, 1 = d: */

/* Warm boot (reboot) device and filename strings */

/*
 * BOOTROM_DIR is the device name for the device containing
 * the bootrom file. This string is used in sysToMonitor, sysLib.c
 * in dosFsDevCreate().
 */

#define BOOTROM_DIR  "/bd0"

/*
 * BOOTROM_BIN is the default path and file name to either a binary
 * bootrom file or an A.OUT file with its 32 byte header stripped.
 * Note that the first part of this string must match BOOTROM_DIR
 * The "bootrom.sys" file name will work with VxLd 1.5.
 */

#define BOOTROM_BIN  BOOTROM_DIR "/bootrom.sys"

/*
 * BOOTROM_AOUT is that default path and file name of an A.OUT bootrom
 * _still containing_ its 32byte A.OUT header.   This is legacy code.
 * Note that the first part of this string must match BOOTROM_DIR
 * The "bootrom.dat" file name does not work with VxLd 1.5.
 */

#define BOOTROM_AOUT BOOTROM_DIR "/bootrom.dat"

/* IDT entry type options */

#define SYS_INT_TRAPGATE    0x0000ef00  /* trap gate */
#define SYS_INT_INTGATE     0x0000ee00  /* int gate */

#ifdef _WRS_CONFIG_SMP
/* SMP must define SYMMETRIC_IO_MODE */

#define SYMMETRIC_IO_MODE       /* Interrupt Mode: Symmetric IO Mode */
#undef  VIRTUAL_WIRE_MODE       /* Virtual Wire Mode NOT Supported on SMP */
#define INCLUDE_HPET            /* SMP requires HPET */
#define USE_HPET_FOR_TIMESTAMP  /* SMP images use HPET for timestamp timer */
#else
#undef  VIRTUAL_WIRE_MODE       /* Interrupt Mode: Virtual Wire Mode */
#undef  SYMMETRIC_IO_MODE       /* Interrupt Mode: Symmetric IO Mode */
#undef  INCLUDE_HPET            /* Optional component if supported by HW */
#endif  /* _WRS_CONFIG_SMP */

#ifndef _WRS_CONFIG_SMP
#undef  USE_HPET_FOR_TIMESTAMP  /* for UP, timestamp driver does not use HPET */
#endif  /* !_WRS_CONFIG_SMP */

#if defined (SYMMETRIC_IO_MODE)
#undef SYS_MODEL
#define SYS_MODEL "Intel(R) ATOM(TM) Platform SYMMETRIC IO"
#elif  defined (VIRTUAL_WIRE_MODE)
#undef SYS_MODEL
#define SYS_MODEL "Intel(R) ATOM(TM) Platform VIRTUAL WIRE"
#endif /* SYMMETRIC_IO_MODE */

#undef  INCLUDE_FD              /* include floppy disk driver */

#ifdef  INCLUDE_DRV_STORAGE_INTEL_AHCI
#   ifdef BOOTAPP
#      define INCLUDE_BOOT_AHCI_LOADER
#      define INCLUDE_BOOT_FILESYSTEMS
#   endif /* BOOTAPP */
#endif /* INCLUDE_DRV_STORAGE_INTEL_AHCI */


#ifdef  INCLUDE_USB
#   define INCLUDE_USB_INIT
#   define INCLUDE_EHCI
#   define INCLUDE_EHCI_INIT
    /* USB OHCI stack is unstable when enabled both in bootloader 
     and image so use it only for image */    
#   ifndef BOOTAPP  
#   	define INCLUDE_OHCI
#   	define INCLUDE_OHCI_INIT
#   endif    
#   define INCLUDE_USB_MS_BULKONLY
#   define INCLUDE_USB_MS_BULKONLY_INIT
#endif

#if defined(INCLUDE_USB) || defined(INCLUDE_DRV_STORAGE_INTEL_AHCI) \
	|| defined(DRV_STORAGE_SI31XX)
#   define INCLUDE_DOSFS
#   define INCLUDE_DOSFS_MAIN
#   define INCLUDE_DOSFS_CHKDSK
#   define INCLUDE_DOSFS_FMT
#   define INCLUDE_RAWFS           /* include raw FS */
#   define INCLUDE_DOSFS_FAT       /* required for DosFs */
#   define INCLUDE_DOSFS_DIR_VFAT
#   define INCLUDE_FS_MONITOR
#   define INCLUDE_FS_EVENT_UTIL   /* include file event utility */
#   define INCLUDE_ERF
#   define INCLUDE_XBD
#   define INCLUDE_XBD_BLK_DEV
#   define INCLUDE_DEVICE_MANAGER
#   define INCLUDE_XBD_PART_LIB
#endif


#undef  INCLUDE_LPT             /* include parallel port driver */

#undef  INCLUDE_TFFS            /* include TrueFFS driver for Flash */

#undef  INCLUDE_HRFS            /* include HRFS file system */

#define INCLUDE_ERF             /* include event report framework */
#define INCLUDE_DEVICE_MANAGER  /* include device manager */

/* VxBus configuration */

#define INCLUDE_VXBUS

#undef INCLUDE_HWCONF  /* usrDepend.c includes hwconf.c */

#ifdef  INCLUDE_VXBUS
    /* VxBus util */

#   define VXBUS_TABLE_CONFIG
#   define INCLUDE_VXB_CMDLINE
#   define INCLUDE_SIO_UTILS
#   define INCLUDE_HWMEM_ALLOC
#   define HWMEM_POOL_SIZE  100000
#   define INCLUDE_PARAM_SYS
#   define INCLUDE_DMA_SYS
#   undef  INCLUDE_NON_VOLATILE_RAM

    /* VxBus bus types */

#   define INCLUDE_PLB_BUS
#   define INCLUDE_PCI_BUS
#   define INCLUDE_PCI

#   if defined (VIRTUAL_WIRE_MODE) || defined (SYMMETRIC_IO_MODE)

/* PCI_IO_ADRS must not overlap APIC... */

#       ifdef PCI_IO_ADRS
#           undef PCI_IO_ADRS
#       endif /* PCI_IO_ADRS */

#       ifdef PCI_IO_SIZE
#           undef PCI_IO_SIZE
#       endif /* PCI_IO_SIZE */

#       define PCI_IO_ADRS 0xa0000000
#       define PCI_IO_SIZE 0x58000000

#   else  /* VIRTUAL_WIRE_MODE || SYMMETRIC_IO_MODE */

#       ifndef PCI_IO_ADRS
#           define PCI_IO_ADRS 0xa0000000
#           define PCI_IO_SIZE 0x5ff80000
#       endif /* PCI_IO_ADRS */

#   endif /* VIRTUAL_WIRE_MODE || SYMMETRIC_IO_MODE */

    /* VxBus drivers */

#   define INCLUDE_PENTIUM_PCI
#   define INCLUDE_PCI_OLD_CONFIG_ROUTINES
#   define DRV_SIO_NS16550
#   undef  DRV_NVRAM_FILE


    /* Network driver options: VxBus drivers */

#   define INCLUDE_GEI825XX_VXB_END
    
    /* PHY and MII bus support */

#   define INCLUDE_MII_BUS
#   define INCLUDE_GENERICPHY

#endif /* INCLUDE_VXBUS */

#define INCLUDE_END             /* Enhanced Network Driver Support */
#define INCLUDE_END2            /* Enhanced Network Driver Support */
#define INCLUDE_NETWORK

/* default MMU options and PHYS_MEM_DESC type state constants */

#define INCLUDE_MMU_BASIC       /* bundled MMU support */
#undef  VM_PAGE_SIZE            /* page size */
#define VM_PAGE_SIZE        PAGE_SIZE_4KB   /* default page size */

#define VM_STATE_MASK_FOR_ALL   \
        VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE
#define VM_STATE_FOR_IO         \
        VM_STATE_VALID      | VM_STATE_WRITABLE      | VM_STATE_CACHEABLE_NOT
#define VM_STATE_FOR_MEM_OS     \
        VM_STATE_VALID      | VM_STATE_WRITABLE      | VM_STATE_CACHEABLE
#define VM_STATE_FOR_MEM_APPLICATION \
        VM_STATE_VALID      | VM_STATE_WRITABLE      | VM_STATE_CACHEABLE
#define VM_STATE_FOR_PCI        \
        VM_STATE_VALID      | VM_STATE_WRITABLE      | VM_STATE_CACHEABLE_NOT

/* CPU family/type-specific macros and options */

#   undef	INCLUDE_SW_FP           /* Pentium4 has hardware FPP */
#   undef	USER_D_CACHE_MODE       /* Pentium4 write-back data cache support */
#   define USER_D_CACHE_MODE   (CACHE_COPYBACK | CACHE_SNOOP_ENABLE)
#   define INCLUDE_MTRR_GET        /* get MTRR to sysMtrr[] */
#   define INCLUDE_PMC             /* include PMC */

#   if defined (VIRTUAL_WIRE_MODE) || defined (SYMMETRIC_IO_MODE)
#       define DRV_INTCTLR_MPAPIC
#       define DRV_INTCTLR_LOAPIC

        /* MSI: define INCLUDE_INTCTLR_DYNAMIC_LIB */

#       define INCLUDE_INTCTLR_DYNAMIC_LIB
#       if defined (SYMMETRIC_IO_MODE)
#           define DRV_INTCTLR_IOAPIC
#       endif /* defined (SYMMETRIC_IO_MODE) */
#   endif /* defined (VIRTUAL_WIRE_MODE) || (SYMMETRIC_IO_MODE) */

#   define INCLUDE_MMU_P6_32BIT    /* include 32bit MMU for Pentium[234] */

#   ifdef  INCLUDE_MMU_P6_32BIT
#      undef  VM_PAGE_SIZE         /* page size could be 4KB, 4MB */
#      define VM_PAGE_SIZE     PAGE_SIZE_4KB   /* PAGE_SIZE_4MB */
#   endif  /* INCLUDE_MMU_P6_32BIT */

#   ifdef  INCLUDE_MMU_P6_36BIT
#      undef  VM_PAGE_SIZE         /* page size could be 4KB, 2MB */
#      define VM_PAGE_SIZE     PAGE_SIZE_4KB   /* PAGE_SIZE_2MB */
#   endif  /* INCLUDE_MMU_P6_32BIT */

#   if defined (INCLUDE_MMU_P6_32BIT) || defined (INCLUDE_MMU_P6_36BIT)
#      undef  VM_STATE_MASK_FOR_ALL
#      undef  VM_STATE_FOR_IO
#      undef  VM_STATE_FOR_MEM_OS
#      undef  VM_STATE_FOR_MEM_APPLICATION
#      undef  VM_STATE_FOR_PCI
#      define VM_STATE_MASK_FOR_ALL \
          VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | \
          VM_STATE_MASK_WBACK | VM_STATE_MASK_GLOBAL
#      define VM_STATE_FOR_IO \
          VM_STATE_VALID | VM_STATE_WRITABLE | \
          VM_STATE_CACHEABLE_NOT | VM_STATE_GLOBAL_NOT
#      define VM_STATE_FOR_MEM_OS \
          VM_STATE_VALID | VM_STATE_WRITABLE | \
          VM_STATE_WBACK | VM_STATE_GLOBAL_NOT
#      define VM_STATE_FOR_MEM_APPLICATION \
          VM_STATE_VALID | VM_STATE_WRITABLE | \
          VM_STATE_WBACK | VM_STATE_GLOBAL_NOT
#      define VM_STATE_FOR_PCI \
          VM_STATE_VALID | VM_STATE_WRITABLE | \
          VM_STATE_CACHEABLE_NOT | VM_STATE_GLOBAL_NOT
#   endif  /* defined (INCLUDE_MMU_P6_32BIT) || defined (INCLUDE_MMU_P6_36BIT) */

#if (defined (VIRTUAL_WIRE_MODE) || defined (SYMMETRIC_IO_MODE))

#      undef  INCLUDE_DEBUG_STORE      /* Debug Store (BTS/PEBS) */
#      ifdef  INCLUDE_DEBUG_STORE
#          define DS_SYS_MODE   FALSE  /* TRUE system mode, FALSE task mode */
#          define BTS_ENABLED   TRUE   /* BTS TRUE enable, FALSE disable */
#          define BTS_INT_MODE  TRUE   /* BTS TRUE int mode, FALSE circular */
#          define BTS_BUF_MODE  TRUE   /* BTS TRUE buffer mode, FALSE bus */
#          define PEBS_ENABLED  TRUE   /* PEBS TRUE enable, FALSE disable */
#          define PEBS_EVENT    PEBS_REPLAY        /* PEBS event */
#          define PEBS_METRIC   PEBS_2NDL_CACHE_LOAD_MISS  /* PEBS metric */
#          define PEBS_OS       TRUE   /* PEBS TRUE supervisor, FALSE usr */
#          define PEBS_RESET    -1LL   /* PEBS default reset counter value */
#      endif /* INCLUDE_DEBUG_STORE */
#endif  /* (defined (VIRTUAL_WIRE_MODE) || defined (SYMMETRIC_IO_MODE)) */


/* vxbus timer specific macros */

#define INCLUDE_TIMER_SYS     /* timer drv control via vxBus */
    
#if defined (SYMMETRIC_IO_MODE)
#   define DRV_TIMER_LOAPIC        /* SMP TIMER DRV */
#define DRV_TIMER_IA_TIMESTAMP  /* SMP will need HPET for timestamp */
#   undef  DRV_TIMER_I8253         /* MODE requires use of Local APIC */
#undef  INCLUDE_AUX_CLK         /* SMP does not support AUX Clock */
#   elif  defined (VIRTUAL_WIRE_MODE)
#   define DRV_TIMER_I8253         /* UP TIMER DRV */
#   define DRV_TIMER_LOAPIC        /* MODE requires use of Local APIC as well */
#   else
#   define DRV_TIMER_I8253         /* UP TIMER DRV */
#   undef  DRV_TIMER_LOAPIC        /* APICS Not initialized in UP */
#endif /* defined (SYMMETRIC_IO_MODE) */

#ifdef INCLUDE_TIMESTAMP
#   define DRV_TIMER_IA_TIMESTAMP
#endif /* INCLUDE_TIMESTAMP */

#ifdef INCLUDE_AUX_CLK
#   define DRV_TIMER_MC146818
#endif /* INCLUDE_AUX_CLK */

/* default system and auxiliary clock constants
 *
 * Among other things, SYS_CLK_RATE_MAX depends upon the CPU and application
 * work load.  The default value, chosen in order to pass the internal test
 * suite, could go up to PIT_CLOCK.
 */

#define SYS_CLK_RATE_MIN        (19)   /* minimum system clock rate */
#define SYS_CLK_RATE_MAX        (5000) /* maximum system clock rate */

#ifdef DRV_TIMER_LOAPIC
#   define AUX_CLK_RATE_MIN     SYS_CLK_RATE_MIN/* min auxiliary clock rate */
#   define AUX_CLK_RATE_MAX     SYS_CLK_RATE_MAX /* max auxiliary clock rate */
#else
#   define AUX_CLK_RATE_MIN     (2)    /* minimum auxiliary clock rate */
#   define AUX_CLK_RATE_MAX     (8192)/* maximum auxiliary clock rate */
#endif /* DRV_TIMER_LOAPIC */

/*
 * ATA_TYPE <ataTypes[][]> ATA_GEO_FORCE parameters
 *
 * ATA_TYPE is defined in h/drv/hdisk/ataDrvK.h.  The <ataTypes[][]> table
 * is declared in sysLib.c.
 */

/* controller zero device zero */

#define ATA_CTRL0_DRV0_CYL  (761)   /* ATA 0, device 0 cylinders */
#define ATA_CTRL0_DRV0_HDS  (8)     /* ATA 0, device 0 heads */
#define ATA_CTRL0_DRV0_SPT  (39)    /* ATA 0, device 0 sectors per track */
#define ATA_CTRL0_DRV0_BPS  (512)   /* ATA 0, device 0 bytes per sector */
#define ATA_CTRL0_DRV0_WPC  (0xff)  /* ATA 0, device 0 write pre-compensation */

/* controller zero device one */

#define ATA_CTRL0_DRV1_CYL  (761)   /* ATA 0, device 1 cylinders */
#define ATA_CTRL0_DRV1_HDS  (8)     /* ATA 0, device 1 heads */
#define ATA_CTRL0_DRV1_SPT  (39)    /* ATA 0, device 1 sectors per track */
#define ATA_CTRL0_DRV1_BPS  (512)   /* ATA 0, device 1 bytes per sector */
#define ATA_CTRL0_DRV1_WPC  (0xff)  /* ATA 0, device 1 write pre-compensation */


/*
 * ATA_RESOURCE <ataResources[]> parameters
 *
 * ATA_RESOURCES is defined in h/drv/pcmcia/pccardLib.h.  The <ataResources[]>
 * table is declared in sysLib.c.  Defaults are based on the pcPentium BSP.
 */

/* ATA controller zero ataResources[] parameters */

#define ATA0_VCC          (5)          /* ATA 0 Vcc (3 or 5 volts) */
#define ATA0_VPP          (0)          /* ATA 0 Vpp (5 or 12 volts or 0) */
#define ATA0_IO_START0    (0x1f0)      /* Start I/O Address 0 for ATA 0 */
#define ATA0_IO_START1    (0x3f6)      /* Start I/O Address 1 for ATA 0 */
#define ATA0_IO_STOP0     (0x1f7)      /* Stop I/O Address for ATA 0 */
#define ATA0_IO_STOP1     (0x3f7)      /* Stop I/O Address for ATA 0 */
#define ATA0_EXTRA_WAITS  (0)          /* ATA 0 extra wait states (0-2) */
#define ATA0_MEM_START    (0)          /* ATA 0 memory start address */
#define ATA0_MEM_STOP     (0)          /* ATA 0 memory start address */
#define ATA0_MEM_WAITS    (0)          /* ATA 0 memory extra wait states */
#define ATA0_MEM_OFFSET   (0)          /* ATA 0 memory offset */
#define ATA0_MEM_LENGTH   (0)          /* ATA 0 memory offset */
#define ATA0_CTRL_TYPE    (IDE_LOCAL)  /* ATA 0 logical type */
#define ATA0_NUM_DRIVES   (1)          /* ATA 0 number drives present */
#define ATA0_INT_LVL      (0x0e)       /* ATA 0 interrupt level */

#define ATA0_CONFIG       (ATA_GEO_CURRENT | ATA_PIO_AUTO | ATA_DMA_AUTO |\
                           ATA_BITS_16     | ATA_PIO_MULTI)

#define ATA0_SEM_TIMEOUT  (5)          /* ATA 0 sync. semaphore timeout */
#define ATA0_WDG_TIMEOUT  (5)          /* ATA 0 watchdog timer timeout */
#define ATA0_SOCKET_TWIN  (0)          /* Socket number (TWIN PCMCIA Card) */
#define ATA0_POWER_DOWN   (0)          /* ATA power down mode */


/* console definitions  */

#undef  NUM_TTY
#define NUM_TTY       (N_UART_CHANNELS)  /* number of tty channels */

#ifdef  INCLUDE_PC_CONSOLE
#   define PC_CONSOLE           (0)      /* console number */
#   define N_VIRTUAL_CONSOLES   (2)      /* shell / application */
#   ifdef INCLUDE_VXBUS
#       define DRV_KBD_I8042
#       define DRV_VGA_M6845
#   endif /* INCLUDE_VXBUS */
#   ifdef  INCLUDE_USB
#   	define INCLUDE_USB_KEYBOARD
#   	define INCLUDE_USB_KEYBOARD_INIT
#   	ifdef BOOTAPP
#		define INCLUDE_USB_KEYBOARD_BOOTSHELL_ATTACH
#   	else
#		define INCLUDE_USB_KEYBOARD_SHELL_ATTACH
#	endif /* BOOTAPP */
#   endif /* INCLUDE_USB */
#endif /* INCLUDE_PC_CONSOLE */

/* PS/2 101-key default keyboard type (use PC_XT_83_KBD for 83-key) */

#define PC_KBD_TYPE   (USB_KBD)

/* memory addresses, offsets, and size constants */

#if (SYS_WARM_TYPE == SYS_WARM_BIOS)            /* non-volatile RAM size */
#   define NV_RAM_SIZE          (NONE)
#else
#   define NV_RAM_SIZE          (0x1000)
#endif /* SYS_WARM_TYPE == SYS_WARM_BIOS */

#define LOCAL_MEM_LOCAL_ADRS    (0x00100000)    /* on-board memory base */
#define USER_RESERVED_MEM       (0)             /* user reserved memory */

/*
 * LOCAL_MEM_SIZE is the offset from the start of on-board memory to the
 * top of memory.  If the page size is 2MB or 4MB, write-protected pages
 * for the MMU directory tables and <globalPageBlock> array are also a
 * multiple of 2MB or 4MB.  Thus, LOCAL_MEM_SIZE should be big enough to
 * hold them.
 */

#define SYSTEM_RAM_SIZE      (0x30000000)    /* Atom Platform minimum 0.75GB system RAM */

#define LOCAL_MEM_SIZE          (SYSTEM_RAM_SIZE - LOCAL_MEM_LOCAL_ADRS)

/*
 * Memory auto-sizing is supported when this option is defined.
 * See sysPhysMemTop() in the BSP sysLib.c file.
 */

#   define   LOCAL_MEM_AUTOSIZE

/*
 * The following parameters are defined here and in the BSP Makefile.
 * They must be kept synchronized.  Any changes made here must be made
 * in the Makefile and vice versa.
 */

#ifdef  BOOTCODE_IN_RAM
/*
#   undef  ROMSTART_BOOT_CLEAR
*/
#   define ROM_BASE_ADRS        (0x00008000)    /* base address of ROM */
#   define ROM_TEXT_ADRS        (ROM_BASE_ADRS) /* booting from A: or C: */
#   define ROM_SIZE             (0x00090000)    /* size of ROM */
#else
#   define ROM_BASE_ADRS        (0xfff20000)    /* base address of ROM */
#   define ROM_TEXT_ADRS        (ROM_BASE_ADRS) /* booting from EPROM */
#   define ROM_SIZE             (0x0007fe00)    /* size of ROM */
#endif /* BOOTCODE_IN_RAM */

#ifdef RAM_LOW_ADRS
#define SYS_RAM_LOW_ADRS        RAM_LOW_ADRS    /* VxWorks image entry point */
#else /* RAM_LOW_ADRS */
#define SYS_RAM_LOW_ADRS        (0x00408000)    /* VxWorks image entry point */
#endif /* RAM_LOW_ADRS */

#ifdef RAM_HIGH_ADRS
#define SYS_RAM_HIGH_ADRS       RAM_HIGH_ADRS   /* Boot image entry point */
#else /* RAM_HIGH_ADRS */
#define SYS_RAM_HIGH_ADRS       (0x04008000)    /* Boot image entry point */
#endif /* RAM_HIGH_ADRS */

/* power management definitions */

#undef  VX_POWER_MANAGEMENT /* define to enable */
#define VX_POWER_MODE_DEFAULT   VX_POWER_MODE_AUTOHALT  /* set mode */
#undef  INCLUDE_CPU_PWR_MGMT

/* interrupt mode/number definitions */

#include "configInum.h"

#define _WRS_BSP_VM_PAGE_OFFSET (VM_PAGE_SIZE)

#ifdef __cplusplus
}
#endif

#endif  /* __INCconfigh */

#if defined(PRJ_BUILD)
#   include "prjParams.h"
#endif

