/*[CR]*************************************************************************
  
  Copyright (c) 2001 - 2003 by PEP Modular Computers GmbH

  All Rights reserved.

*/
/*[FH]*************************************************************************
  FILE:     lm81_hw.h
  MODULE:   LM81
  CMM ID:   $ID$
  CONTENTS: Header for the LM81 ACPI hardware monitor (SMBus) library
*/

#ifndef LM81_HW_H
#define LM81_HW_H

#ifdef __cplusplus
extern "C" {
#endif

/* includes */

/* defines */

/* SMBus address definitions */
#define	LM81_ADDR1			0x2c	/* address of 1st LM81 on PEP boards */
#define LM81_ADDR_START		0x2c
#define LM81_ADDR_END		0x2f
#define LM81_ADDR_MASK		0x03	/* mask SMB address to access array */


/* defintions to select thresholds */
#define LM81_LOW			0		/* select low threshold */
#define LM81_HIGH			1		/* select high threshold */
#define LM81_HYST			2		/* temperature hysteresis */

/* definitions for hysteresis */
#define LM81_HYST_MIN		0
#define LM81_HYST_MAX		7

/* definitions for temperature handling */
#define LM81_TEMP_MAX		127
#define LM81_TEMP_MIN		(-55)

/* definitions for voltage handling */
#define	LM81_V1				0		/* measure at VCCP1 pin */
#define	LM81_V2				1		/* measure at +2.5V pin */
#define	LM81_V3				2		/* measure at +3.3V pin */
#define	LM81_V4				3		/* measure at +5.0V pin */
#define	LM81_V5				4		/* measure at +12V  pin */
#define	LM81_V6				5		/* measure at VCCP2 pin */

/* definitions for fan handling */
#define	LM81_FAN1			0		/* measure at FAN1 pin */
#define	LM81_FAN2			1		/* measure at FAN2 pin */
#define	LM81_DIV1			0		/* FAN count divisor 1 */
#define	LM81_DIV2			1		/* FAN count divisor 2 */
#define	LM81_DIV4			2		/* FAN count divisor 4 */
#define	LM81_DIV8			3		/* FAN count divisor 8 */

/* definitions for power supply management */
#define LM81_V1_LSB			(14.1*1e-3)
#define LM81_V2_LSB			(13.0*1e-3)
#define LM81_V3_LSB			(17.2*1e-3)
#define LM81_V4_LSB			(26.0*1e-3)
#define LM81_V5_LSB			(62.5*1e-3)
#define LM81_V6_LSB			(-59.0*1e-3)

/* register offsets */
#define	LM81_CFG			0x40	/* configuration register */
#define	LM81_ISR1			0x41	/* interrupt status register 1 */
#define	LM81_ISR2			0x42	/* interrupt status register 2 */
#define	LM81_IMR1			0x43	/* interrupt mask register 1 */
#define	LM81_IMR2			0x44	/* interrupt mask register 2 */
#define	LM81_CICL			0x46	/* CI clear register */
#define	LM81_VIDF			0x47	/* VID/Fan divisor register */
#define	LM81_SBADR			0x48	/* serial bus address register */
#define	LM81_VID4			0x49	/* VID4 register */
#define	LM81_TCFG			0x4b	/* temperature configuration register */
#define	LM81_EMR1			0x4c	/* extended mode register 1 */
#define	LM81_EMR2			0x4d	/* extended mode register 2 */

/* parameter ram offsets */
#define	LM81_VRDAC			0x19	/* DAC data register address */
#define	LM81_RAM_2V5		0x20	/* 2.5V value address */
#define	LM81_RAM_VCCP1		0x21	/* Vccp1 value address */
#define	LM81_RAM_3V3		0x22	/* 3.3V value address */
#define	LM81_RAM_5V			0x23	/* 5V value address */
#define	LM81_RAM_12V		0x24	/* 12V value address */
#define	LM81_RAM_VCCP2		0x25	/* Vccp2 value address */
#define	LM81_RAM_TEMP		0x27	/* temperature value address */
#define	LM81_RAM_FAN1		0x28	/* FAN1 counter value address */
#define	LM81_RAM_FAN2		0x29	/* FAN2 counter value address */

#define	LM81_RAM_2V5_HL		0x2b	/* 2.5V high limit address */
#define	LM81_RAM_2V5_LL		0x2c	/* 2.5V low limit address */
#define	LM81_RAM_VCCP1_HL	0x2d	/* Vccp1 high limit address */
#define	LM81_RAM_VCCP1_LL	0x2e	/* Vccp1 low limit address */
#define	LM81_RAM_3V3_HL		0x2f	/* 3.3V high limit address */
#define	LM81_RAM_3V3_LL		0x30	/* 3.3V low limit address */
#define	LM81_RAM_5V_HL		0x31	/* 5V high limit address */
#define	LM81_RAM_5V_LL		0x32	/* 5V low limit address */
#define	LM81_RAM_12V_HL		0x33	/* 12V high limit address */
#define	LM81_RAM_12V_LL		0x34	/* 12V low limit address */
#define	LM81_RAM_VCCP2_HL	0x35	/* Vccp2 high limit address */
#define	LM81_RAM_VCCP2_LL	0x36	/* Vccp2 low limit address */
#define	LM81_RAM_TEMP_CIRT	0x37	/* temperature T_CIRT address */
#define	LM81_RAM_TEMP_LL	0x38	/* temperature low limit address */
#define	LM81_RAM_TEMP_HL	0x39	/* temperature high limit address */
#define	LM81_RAM_TEMP_HYST	0x3a	/* temperature hysteresis limit address */
#define	LM81_RAM_FAN1_LL	0x3b	/* FAN1 counter low limit address */
#define	LM81_RAM_FAN2_LL	0x3c	/* FAN2 counter low limit address */

/* configuration register bits */
#define	LM81_CFG_START		0x01	/* start monitoring */
#define	LM81_CFG_INIT		0x80	/* set LM81 to POR state */
#define	LM81_CFG_INTCLR		0x08	/* clear INT bit / resume monitoring */

/* interrupt status register 1 bits */
#define	LM81_ISR1_V1		0x01	/* 2.5V high/low limit exceeded */
#define	LM81_ISR1_V2		0x02	/* Vccp1 high/low limit exceeded */
#define	LM81_ISR1_V3		0x04	/* 3.3V high/low limit exceeded */
#define	LM81_ISR1_V4		0x08	/* 5V high/low limit exceeded */
#define	LM81_ISR1_TEMP		0x10	/* temperature high/low limit exceeded */
#define	LM81_ISR1_FAN1		0x40	/* FAN1 count limit exceeded */
#define	LM81_ISR1_FAN2		0x80	/* FAN2 count limit exceeded */

/* interrupt status register 2 bits */
#define	LM81_ISR2_V5		0x01	/* +12V high/low limit exceeded */
#define	LM81_ISR2_V6		0x02	/* Vccp2 high/low limit exceeded */
#define	LM81_ISR2_TLOW		0x80	/* temperature low limit exceeded */

/* temperature configuration register bits */
#define LM81_TCFG_MODE_MSK	0xfc	/* mode mask */
#define LM81_TCFG_CM		0x02	/* comparator mode */

/* extended mode register 1 bits */
#define	LM81_EMR1_EME		0x01	/* extended mode enable */

/* extended mode register 2 bits */
#define	LM81_EMR2_HYST_MSK	0xf8	/* hyst mask */

/* function declarations */

#ifdef __cplusplus
}
#endif

#endif /* LM81_HW_H */
