<?xml version="1.0" encoding="UTF-8"?>

<pin_planner>
	<pin_info>
		<pin name="clk_100MHz_pcie5" direction="Input" source="Hierarchy Database" diff_pair_node="clk_100MHz_pcie5(n)" >
		</pin>
		<pin name="rx_in" direction="Input" source="Hierarchy Database" diff_pair_node="rx_in(n)" >
		</pin>
		<pin name="tx_out" direction="Output" source="Hierarchy Database" diff_pair_node="tx_out(n)" >
		</pin>
		<pin name="clk_100MHz_pcie5(n)" direction="Input" source="Assignments" diff_pair_node="clk_100MHz_pcie5" >
		</pin>
		<pin name="rx_in(n)" direction="Input" source="Assignments" diff_pair_node="rx_in" >
		</pin>
		<pin name="tx_out(n)" direction="Output" source="Assignments" diff_pair_node="tx_out" >
		</pin>
	</pin_info>
	<buses>
	</buses>
	<group_file_association>
	</group_file_association>
	<pin_planner_file_specifies>
	</pin_planner_file_specifies>
</pin_planner>
