msmst_test |

2011.03.07.18:29:51 | Datasheet

Overview

| pcie0
| pcie_rstn
| phystatus_ext
| rx_in0
| refclk
| rxdata0_ext
| reconfig_clk
| reconfig_togxb
| gxb_powerdown
| pll_powerdown
| fixedclk_serdes
| busy_altgxb_reconfig
| rxdatak0_ext
| rxelecidle0_ext
| rxstatus0_ext
| rxvalid0_ext
| test_in
| pipe_mode
| clk125_out
| tx_out0
| powerdown_ext
| rxpolarity0_ext
| reconfig_fromgxb
| clk250_out
| clk500_out
| rate_ext
| txcompl0_ext
| txdata0_ext
| txdatak0_ext
| txdetectrx_ext
| txelecidle0_ext
| gpio_west
| bidir_port
| bidir_port
| out_port
| in_port
| bidir_port
| bidir_port
| bidir_port
| bidir_port
| in_port
| bidir_port

All Components
pcie0 altera_avalon_pcie_compiler 10.1.197
gpio_west altera_avalon_pio 10.1
gpio_east altera_avalon_pio 10.1
hsmc_misc_out altera_avalon_pio 10.1
hsmc_misc_in altera_avalon_pio 10.1
hsmc_bank2_west altera_avalon_pio 10.1
hsmc_bank2_east altera_avalon_pio 10.1
hsmc_bank3_west altera_avalon_pio 10.1
hsmc_bank3_east altera_avalon_pio 10.1
lpcpod_in altera_avalon_pio 10.1
hsmc_misc_io altera_avalon_pio 10.1
dma_0 altera_avalon_dma 10.1
Memory Map

| pcie0 | dma_0
bar0_Non_Prefetchable | bar1_Non_Prefetchable | read_master | write_master
pcie0 |  |  |  |
Control_Register_Access |  | 0x80000000 |  |
Tx_Interface |  |  | 0x00000000 | 0x00000000
gpio_west |  |  |  |
s1 | 0x80004100 |  |  |
gpio_east |  |  |  |
s1 | 0x80004180 |  |  |
hsmc_misc_out |  |  |  |
s1 | 0x80004280 |  |  |
hsmc_misc_in |  |  |  |
s1 | 0x80004200 |  |  |
hsmc_bank2_west |  |  |  |
s1 | 0x80004380 |  |  |
hsmc_bank2_east |  |  |  |
s1 | 0x80004400 |  |  |
hsmc_bank3_west |  |  |  |
s1 | 0x80004480 |  |  |
hsmc_bank3_east |  |  |  |
s1 | 0x80004500 |  |  |
lpcpod_in |  |  |  |
s1 | 0x80004580 |  |  |
hsmc_misc_io |  |  |  |
s1 | 0x80004300 |  |  |
dma_0 |  |  |  |
control_port_slave |  | 0x80004000 |  |

## pcie0

altera_avalon_pcie_compiler v10.1.197

dma_0 | write_master | pcie0
Tx_Interface
read_master
Tx_Interface
|  | pcie_core_clk | gpio_west
|  | clk
|  | bar0_Non_Prefetchable
|  | s1
|  | pcie_core_clk | gpio_east
|  | clk
|  | bar0_Non_Prefetchable
|  | s1
|  | pcie_core_clk | hsmc_misc_in
|  | clk
|  | bar0_Non_Prefetchable
|  | s1
|  | pcie_core_clk | hsmc_bank2_west
|  | clk
|  | bar0_Non_Prefetchable
|  | s1
|  | pcie_core_clk | hsmc_bank2_east
|  | clk
|  | bar0_Non_Prefetchable
|  | s1
|  | pcie_core_clk | hsmc_bank3_west
|  | clk
|  | bar0_Non_Prefetchable
|  | s1
|  | pcie_core_clk | hsmc_bank3_east
|  | clk
|  | bar0_Non_Prefetchable
|  | s1
|  | pcie_core_clk | lpcpod_in
|  | clk
|  | bar0_Non_Prefetchable
|  | s1
|  | pcie_core_clk | hsmc_misc_out
|  | clk
|  | bar0_Non_Prefetchable
|  | s1
|  | pcie_core_clk | hsmc_misc_io
|  | clk
|  | bar0_Non_Prefetchable
|  | s1
|  | pcie_core_clk | dma_0
|  | clk
|  | RxmIrq
|  | irq
|  | bar1_Non_Prefetchable
|  | control_port_slave

## Parameters
SOPCSystemName | msmst_test
actualBAR0AvalonAddress | 2147500032
actualBAR0Size | 11
actualBAR1AvalonAddress | 2147483648
actualBAR1Size | 15
actualBAR2AvalonAddress | 0
actualBAR2Size | 0
actualBAR3AvalonAddress | 0
actualBAR3Size | 0
actualBAR4AvalonAddress | 0
actualBAR4Size | 0
actualBAR5AvalonAddress | 0
actualBAR5Size | 0
allowedDeviceFamilies |
altgx_generated | 0
clockSource | pcie_core_clk
contextState | SOPCContext
deviceFamily | Arria II GX
ordering_code | IP-PCIE/4
p_avalon_hardwired_address_map | true
p_avalon_hw_pci_address_00 | 0x0000000000000000
p_avalon_hw_pci_address_00_type | Memory32Bit
p_avalon_hw_pci_address_01 | 0x0000000000000000
p_avalon_hw_pci_address_01_type | Memory32Bit
p_avalon_hw_pci_address_02 | 0x0000000000000000
p_avalon_hw_pci_address_02_type | Memory32Bit
p_avalon_hw_pci_address_03 | 0x0000000000000000
p_avalon_hw_pci_address_03_type | Memory32Bit
p_avalon_hw_pci_address_04 | 0x0000000000000000
p_avalon_hw_pci_address_04_type | Memory32Bit
p_avalon_hw_pci_address_05 | 0x0000000000000000
p_avalon_hw_pci_address_05_type | Memory32Bit
p_avalon_hw_pci_address_06 | 0x0000000000000000
p_avalon_hw_pci_address_06_type | Memory32Bit
p_avalon_hw_pci_address_07 | 0x0000000000000000
p_avalon_hw_pci_address_07_type | Memory32Bit
p_avalon_hw_pci_address_08 | 0x0000000000000000
p_avalon_hw_pci_address_08_type | Memory32Bit
p_avalon_hw_pci_address_09 | 0x0000000000000000
p_avalon_hw_pci_address_09_type | Memory32Bit
p_avalon_hw_pci_address_10 | 0x0000000000000000
p_avalon_hw_pci_address_10_type | Memory32Bit
p_avalon_hw_pci_address_11 | 0x0000000000000000
p_avalon_hw_pci_address_11_type | Memory32Bit
p_avalon_hw_pci_address_12 | 0x0000000000000000
p_avalon_hw_pci_address_12_type | Memory32Bit
p_avalon_hw_pci_address_13 | 0x0000000000000000
p_avalon_hw_pci_address_13_type | Memory32Bit
p_avalon_hw_pci_address_14 | 0x0000000000000000
p_avalon_hw_pci_address_14_type | Memory32Bit
p_avalon_hw_pci_address_15 | 0x0000000000000000
p_avalon_hw_pci_address_15_type | Memory32Bit
p_avalon_pane_count | 1
p_avalon_pane_size | 20
p_enable_pcie_hip_dprio | N/A
p_pci_64bit_bar | false
p_pci_64bit_bus | true
p_pci_66mhz | true
p_pci_allow_param_readback | false
p_pci_altera_arbiter | false
p_pci_arbited_devices | 2
p_pci_arbiter | false
p_pci_bar_0_auto_avalon_address | true
p_pci_bar_0_auto_sized | true
p_pci_bar_0_avalon_address | 0
p_pci_bar_0_hardwired | false
p_pci_bar_0_pci_address | 0
p_pci_bar_0_prefetchable | false
p_pci_bar_1_auto_avalon_address | true
p_pci_bar_1_auto_sized | true
p_pci_bar_1_avalon_address | 0
p_pci_bar_1_hardwired | false
p_pci_bar_1_pci_address | 0
p_pci_bar_1_prefetchable | false
p_pci_bar_2_auto_avalon_address | false
p_pci_bar_2_auto_sized | false
p_pci_bar_2_avalon_address | 0
p_pci_bar_2_hardwired | false
p_pci_bar_2_pci_address | 0
p_pci_bar_2_prefetchable | true
p_pci_bar_3_auto_avalon_address | false
p_pci_bar_3_auto_sized | false
p_pci_bar_3_avalon_address | 0
p_pci_bar_3_hardwired | false
p_pci_bar_3_pci_address | 0
p_pci_bar_3_prefetchable | true
p_pci_bar_4_auto_avalon_address | false
p_pci_bar_4_auto_sized | false
p_pci_bar_4_avalon_address | 0
p_pci_bar_4_hardwired | false
p_pci_bar_4_pci_address | 0
p_pci_bar_4_prefetchable | true
p_pci_bar_5_auto_avalon_address | false
p_pci_bar_5_auto_sized | false
p_pci_bar_5_avalon_address | 0
p_pci_bar_5_hardwired | false
p_pci_bar_5_pci_address | 0
p_pci_bar_5_prefetchable | true
p_pci_bus_access_address_width | 18
p_pci_global_reset | false
p_pci_host_bridge | false
p_pci_impl_cra_av_slave_port | true
p_pci_master | true
p_pci_master_bursts | true
p_pci_master_concurrent_reads | false
p_pci_master_data_width | 64
p_pci_maximum_burst_size | 128
p_pci_maximum_burst_size_a2p | 128
p_pci_maximum_pending_read_transactions_a2p | 8
p_pci_non_pref_av_master_port | true
p_pci_not_target_only_port | false
p_pci_pref_av_master_port | true
p_pci_reqn_gntn_pins | true
p_pci_single_clock | true
p_pci_target_bursts | true
p_pci_target_concurrent_reads | false
p_pci_user_specified_bars | false
p_pcie_L1_exit_latency_common_clock | >64 us
p_pcie_L1_exit_latency_separate_clock | >64 us
p_pcie_advanced_error_int_num | 0x00000000
p_pcie_advanced_error_reporting | false
p_pcie_alt2gxb | true
p_pcie_altgx_keyParameters_used | {p_pcie_enable_hip=1, p_pcie_number_of_lanes=x1, p_pcie_phy=Arria II GX, p_pcie_rate=Gen1 (2.5 Gbps), p_pcie_txrx_clock=100 MHz}
p_pcie_app_signal_interface | AvalonMM
p_pcie_attention_button | false
p_pcie_attention_indicator | false
p_pcie_auto_configure_retry_buffer | true
p_pcie_avalon_mm_lite | 0
p_pcie_bar_size_bar_0 | Auto
p_pcie_bar_size_bar_1 | Auto
p_pcie_bar_size_bar_2 | N/A
p_pcie_bar_size_bar_3 | N/A
p_pcie_bar_size_bar_4 | N/A
p_pcie_bar_size_bar_5 | N/A
p_pcie_bar_type_bar_0 | 32-bit Non-Prefetchable Memory
p_pcie_bar_type_bar_1 | 32-bit Non-Prefetchable Memory
p_pcie_bar_type_bar_2 | Disable this and all higher BARs
p_pcie_bar_type_bar_3 | Disable this and all higher BARs
p_pcie_bar_type_bar_4 | Disable this and all higher BARs
p_pcie_bar_type_bar_5 | Disable this and all higher BARs
p_pcie_bar_used_bar_0 | true
p_pcie_bar_used_bar_1 | true
p_pcie_bar_used_bar_2 | false
p_pcie_bar_used_bar_3 | false
p_pcie_bar_used_bar_4 | false
p_pcie_bar_used_bar_5 | false
p_pcie_channel_number | 0
p_pcie_chk_io | 0
p_pcie_class_code | 0xFF0000
p_pcie_completion_data_credit_vc0 | 256
p_pcie_completion_data_credit_vc1 | 0
p_pcie_completion_data_credit_vc2 | 0
p_pcie_completion_data_credit_vc3 | 0
p_pcie_completion_data_used_space_vc0 | 4096
p_pcie_completion_data_used_space_vc1 | 0
p_pcie_completion_data_used_space_vc2 | 0
p_pcie_completion_data_used_space_vc3 | 0
p_pcie_completion_header_credit_vc0 | 48
p_pcie_completion_header_credit_vc1 | 0
p_pcie_completion_header_credit_vc2 | 0
p_pcie_completion_header_credit_vc3 | 0
p_pcie_completion_header_used_space_vc0 | 768
p_pcie_completion_header_used_space_vc1 | 0
p_pcie_completion_header_used_space_vc2 | 0
p_pcie_completion_header_used_space_vc3 | 0
p_pcie_completion_timeout | NONE
p_pcie_custom_phy_x8 | 0
p_pcie_custom_rx_buffer_xml | 0
p_pcie_device_id | 0x0004
p_pcie_device_init_required | false
p_pcie_disable_L0s | false
p_pcie_dll_active_report_support | false
p_pcie_ecrc_check | false
p_pcie_ecrc_generation | false
p_pcie_eie_b4_nfts_count | 4
p_pcie_enable_L1_aspm | false
p_pcie_enable_completion_timeout_disable | false
p_pcie_enable_fast_recovery | true
p_pcie_enable_function_msix_support | false
p_pcie_enable_hip | 1
p_pcie_enable_hip_core_clk | 0
p_pcie_enable_pcie_gen2_x8_es | 0
p_pcie_enable_pcie_gen2_x8_s5gx | 0
p_pcie_enable_root_port_endpoint_mode | 0
p_pcie_enable_simple_dma | 0
p_pcie_enable_slot_capability | false
p_pcie_enable_tl_bypass_mode | 0
p_pcie_endpoint_L0s_acceptable_latency | <64 ns
p_pcie_endpoint_L1_acceptable_latency | <1 us
p_pcie_exp_rom_bar_size | N/A
p_pcie_exp_rom_bar_used | false
p_pcie_gen2_nfts_diff_clock | 255
p_pcie_gen2_nfts_same_clock | 255
p_pcie_implement_data_register | false
p_pcie_initiator_performance_preset | High
p_pcie_internal_clock | 125 MHz
p_pcie_io_base_and_limit_register | IODisable
p_pcie_lanerev | 0
p_pcie_link_common_clock | true
p_pcie_link_port_number | 0x01
p_pcie_low_priority_virtual_channels | 0
p_pcie_max_payload_size | 128 Bytes
p_pcie_mem_base_and_limit_register | MemDisable
p_pcie_msi_message_64bits_address_capable | true
p_pcie_msi_message_requested | 1
p_pcie_msix_pba_bir | 0
p_pcie_msix_pba_offset | 0
p_pcie_msix_table_bir | 0
p_pcie_msix_table_offset | 0
p_pcie_msix_table_size | 0
p_pcie_nfts_common_clock | 255
p_pcie_nfts_separate_clock | 255
p_pcie_nonposted_data_credit_vc0 | 0
p_pcie_nonposted_data_credit_vc1 | 0
p_pcie_nonposted_data_credit_vc2 | 0
p_pcie_nonposted_data_credit_vc3 | 0
p_pcie_nonposted_data_used_space_vc0 | 0
p_pcie_nonposted_data_used_space_vc1 | 0
p_pcie_nonposted_data_used_space_vc2 | 0
p_pcie_nonposted_data_used_space_vc3 | 0
p_pcie_nonposted_header_credit_vc0 | 20
p_pcie_nonposted_header_credit_vc1 | 0
p_pcie_nonposted_header_credit_vc2 | 0
p_pcie_nonposted_header_credit_vc3 | 0
p_pcie_nonposted_header_used_space_vc0 | 320
p_pcie_nonposted_header_used_space_vc1 | 0
p_pcie_nonposted_header_used_space_vc2 | 0
p_pcie_nonposted_header_used_space_vc3 | 0
p_pcie_number_of_lanes | x1
p_pcie_phy | Arria II GX
p_pcie_phy_interface | Serial
p_pcie_pme_pending | false
p_pcie_pme_reg_id | 0x0000
p_pcie_port_type | Native Endpoint
p_pcie_posted_data_credit_vc0 | 91
p_pcie_posted_data_credit_vc1 | 0
p_pcie_posted_data_credit_vc2 | 0
p_pcie_posted_data_credit_vc3 | 0
p_pcie_posted_data_used_space_vc0 | 1456
p_pcie_posted_data_used_space_vc1 | 0
p_pcie_posted_data_used_space_vc2 | 0
p_pcie_posted_data_used_space_vc3 | 0
p_pcie_posted_header_credit_vc0 | 17
p_pcie_posted_header_credit_vc1 | 0
p_pcie_posted_header_credit_vc2 | 0
p_pcie_posted_header_credit_vc3 | 0
p_pcie_posted_header_used_space_vc0 | 272
p_pcie_posted_header_used_space_vc1 | 0
p_pcie_posted_header_used_space_vc2 | 0
p_pcie_posted_header_used_space_vc3 | 0
p_pcie_power_indicator | false
p_pcie_rate | Gen1 (2.5 Gbps)
p_pcie_rate_match_fifo | true
p_pcie_retry_buffer_size | 2 KBytes
p_pcie_retry_fifo_depth | 64
p_pcie_revision_id | 0x04
p_pcie_rx_buffer_preset | Default
p_pcie_rx_buffer_size_string_vc0 | 6912 Bytes
p_pcie_rx_buffer_size_string_vc1 | 0
p_pcie_rx_buffer_size_string_vc2 | 0
p_pcie_rx_buffer_size_string_vc3 | 0
p_pcie_rx_buffer_size_vc0 | 6912
p_pcie_rx_buffer_size_vc1 | 0
p_pcie_rx_buffer_size_vc2 | 0
p_pcie_rx_buffer_size_vc3 | 0
p_pcie_slot_capabilities | 0x00000000
p_pcie_special_phy_gl | 0
p_pcie_special_phy_px | 1
p_pcie_subsystem_device_id | 0x0004
p_pcie_subsystem_vendor_id | 0x187C
p_pcie_surprise_down_error_support | false
p_pcie_tag_supported | 32
p_pcie_target_performance_preset | High
p_pcie_test_out_width | None
p_pcie_threshold_for_L0s_entry | 8192 ns
p_pcie_total_header_credit_vc0 | 85
p_pcie_total_header_credit_vc1 | 0
p_pcie_total_header_credit_vc2 | 0
p_pcie_total_header_credit_vc3 | 0
p_pcie_txrx_clock | 100 MHz
p_pcie_underSOPCBuilder | true
p_pcie_use_crc_forwarding | false
p_pcie_use_parity | false
p_pcie_variation_name | pcie0_core
p_pcie_vendor_id | 0x187C
p_pcie_version | 1.1
p_pcie_virutal_channels | 1
pref_nonp_independent | false
translationTableSizeInfo | The bridge reserves a contiguous Avalon address range to access PCIe devices. This Avalon address range is segmented into one or more equal-sized pages that are individually mapped to PCIe addresses. Select the number and size of the address pages.
uiAvalonHWAddress0 | 0x00000000
uiAvalonHWAddress1 | 0x00000000
uiAvalonHWAddress10 | 0x00000000
uiAvalonHWAddress11 | 0x00000000
uiAvalonHWAddress12 | 0x00000000
uiAvalonHWAddress13 | 0x00000000
uiAvalonHWAddress14 | 0x00000000
uiAvalonHWAddress15 | 0x00000000
uiAvalonHWAddress2 | 0x00000000
uiAvalonHWAddress3 | 0x00000000
uiAvalonHWAddress4 | 0x00000000
uiAvalonHWAddress5 | 0x00000000
uiAvalonHWAddress6 | 0x00000000
uiAvalonHWAddress7 | 0x00000000
uiAvalonHWAddress8 | 0x00000000
uiAvalonHWAddress9 | 0x00000000
uiAvalonHWPCIAddress0 | 0x00000000
uiAvalonHWPCIAddress1 | 0x00000000
uiAvalonHWPCIAddress10 | 0x00000000
uiAvalonHWPCIAddress11 | 0x00000000
uiAvalonHWPCIAddress12 | 0x00000000
uiAvalonHWPCIAddress13 | 0x00000000
uiAvalonHWPCIAddress14 | 0x00000000
uiAvalonHWPCIAddress15 | 0x00000000
uiAvalonHWPCIAddress2 | 0x00000000
uiAvalonHWPCIAddress3 | 0x00000000
uiAvalonHWPCIAddress4 | 0x00000000
uiAvalonHWPCIAddress5 | 0x00000000
uiAvalonHWPCIAddress6 | 0x00000000
uiAvalonHWPCIAddress7 | 0x00000000
uiAvalonHWPCIAddress8 | 0x00000000
uiAvalonHWPCIAddress9 | 0x00000000
uiAvalonTranslationTable | false
uiBar0PCIAddress | 0x00000000
uiBar0Prefetchable | false
uiBar1PCIAddress | 0x00000000
uiBar1Prefetchable | false
uiBar2PCIAddress | 0x00000000
uiBar2Prefetchable | true
uiBar3PCIAddress | 0x00000000
uiBar3Prefetchable | true
uiBar4PCIAddress | 0x00000000
uiBar4Prefetchable | true
uiBar5PCIAddress | 0x00000000
uiBar5Prefetchable | true
uiCRAInfoPanel | other
uiExpROMType | Select to Enable
uiFixedTable | true
uiPCIBar0Type | 32-bit Non-Prefetchable Memory
uiPCIBar1Type | 32-bit Non-Prefetchable Memory
uiPCIBar2Type | Disable this and all higher BARs
uiPCIBar3Type | Disable this and all higher BARs
uiPCIBar4Type | Disable this and all higher BARs
uiPCIBar5Type | Disable this and all higher BARs
uiPCIBarTable | false
uiPCIBusArbiter | external
uiPCIDeviceMode | masterTarget
uiPCIMasterPerformance | burstSinglePending
uiPCITargetPerformance | burstSinglePending
uiPaneCount | 1
uiPaneSize | 20
ui_pcie_msix_pba_bir | 0
ui_pcie_msix_table_bir | 0
generateLegacySim | false

## Software Assignments (none)

## gpio_west

altera_avalon_pio v10.1

pcie0 | pcie_core_clk | gpio_west
clk
bar0_Non_Prefetchable
s1

## Parameters
bitClearingEdgeCapReg | false
bitModifyingOutReg | false
captureEdge | false
clockRate | 125000000
direction | Bidir
edgeType | RISING
generateIRQ | false
irqType | LEVEL
resetValue | 0
simDoTestBenchWiring | true
simDrivenValue | 0
width | 17
deviceFamily | UNKNOWN
generateLegacySim | false

## Software Assignments
DO_TEST_BENCH_WIRING | 1
DRIVEN_SIM_VALUE | 0x0
HAS_TRI | 1
HAS_OUT | 0
HAS_IN | 0
CAPTURE | 0
BIT_CLEARING_EDGE_REGISTER | 0
BIT_MODIFYING_OUTPUT_REGISTER | 0
DATA_WIDTH | 17
RESET_VALUE | 0x0
EDGE_TYPE | "NONE"
IRQ_TYPE | "NONE"
FREQ | 125000000u

## gpio_east

altera_avalon_pio v10.1

pcie0 | pcie_core_clk | gpio_east
clk
bar0_Non_Prefetchable
s1

## Parameters
bitClearingEdgeCapReg | false
bitModifyingOutReg | false
captureEdge | false
clockRate | 125000000
direction | Bidir
edgeType | RISING
generateIRQ | false
irqType | LEVEL
resetValue | 0
simDoTestBenchWiring | true
simDrivenValue | 0
width | 17
deviceFamily | UNKNOWN
generateLegacySim | false

## Software Assignments
DO_TEST_BENCH_WIRING | 1
DRIVEN_SIM_VALUE | 0x0
HAS_TRI | 1
HAS_OUT | 0
HAS_IN | 0
CAPTURE | 0
BIT_CLEARING_EDGE_REGISTER | 0
BIT_MODIFYING_OUTPUT_REGISTER | 0
DATA_WIDTH | 17
RESET_VALUE | 0x0
EDGE_TYPE | "NONE"
IRQ_TYPE | "NONE"
FREQ | 125000000u

## hsmc_misc_out

altera_avalon_pio v10.1

pcie0 | pcie_core_clk | hsmc_misc_out
clk
bar0_Non_Prefetchable
s1

## Parameters
bitClearingEdgeCapReg | false
bitModifyingOutReg | false
captureEdge | false
clockRate | 125000000
direction | Output
edgeType | RISING
generateIRQ | false
irqType | LEVEL
resetValue | 0
simDoTestBenchWiring | false
simDrivenValue | 0
width | 5
deviceFamily | UNKNOWN
generateLegacySim | false

## Software Assignments
DO_TEST_BENCH_WIRING | 0
DRIVEN_SIM_VALUE | 0x0
HAS_TRI | 0
HAS_OUT | 1
HAS_IN | 0
CAPTURE | 0
BIT_CLEARING_EDGE_REGISTER | 0
BIT_MODIFYING_OUTPUT_REGISTER | 0
DATA_WIDTH | 5
RESET_VALUE | 0x0
EDGE_TYPE | "NONE"
IRQ_TYPE | "NONE"
FREQ | 125000000u

## hsmc_misc_in

altera_avalon_pio v10.1

pcie0 | pcie_core_clk | hsmc_misc_in
clk
bar0_Non_Prefetchable
s1

## Parameters
bitClearingEdgeCapReg | false
bitModifyingOutReg | false
captureEdge | false
clockRate | 125000000
direction | Input
edgeType | RISING
generateIRQ | false
irqType | LEVEL
resetValue | 0
simDoTestBenchWiring | true
simDrivenValue | 0
width | 5
deviceFamily | UNKNOWN
generateLegacySim | false

## Software Assignments
DO_TEST_BENCH_WIRING | 1
DRIVEN_SIM_VALUE | 0x0
HAS_TRI | 0
HAS_OUT | 0
HAS_IN | 1
CAPTURE | 0
BIT_CLEARING_EDGE_REGISTER | 0
BIT_MODIFYING_OUTPUT_REGISTER | 0
DATA_WIDTH | 5
RESET_VALUE | 0x0
EDGE_TYPE | "NONE"
IRQ_TYPE | "NONE"
FREQ | 125000000u

## hsmc_bank2_west

altera_avalon_pio v10.1

pcie0 | pcie_core_clk | hsmc_bank2_west
clk
bar0_Non_Prefetchable
s1

## Parameters
bitClearingEdgeCapReg | false
bitModifyingOutReg | false
captureEdge | false
clockRate | 125000000
direction | Bidir
edgeType | RISING
generateIRQ | false
irqType | LEVEL
resetValue | 0
simDoTestBenchWiring | true
simDrivenValue | 0
width | 18
deviceFamily | UNKNOWN
generateLegacySim | false

## Software Assignments
DO_TEST_BENCH_WIRING | 1
DRIVEN_SIM_VALUE | 0x0
HAS_TRI | 1
HAS_OUT | 0
HAS_IN | 0
CAPTURE | 0
BIT_CLEARING_EDGE_REGISTER | 0
BIT_MODIFYING_OUTPUT_REGISTER | 0
DATA_WIDTH | 18
RESET_VALUE | 0x0
EDGE_TYPE | "NONE"
IRQ_TYPE | "NONE"
FREQ | 125000000u

## hsmc_bank2_east

altera_avalon_pio v10.1

pcie0 | pcie_core_clk | hsmc_bank2_east
clk
bar0_Non_Prefetchable
s1

## Parameters
bitClearingEdgeCapReg | false
bitModifyingOutReg | false
captureEdge | false
clockRate | 125000000
direction | Bidir
edgeType | RISING
generateIRQ | false
irqType | LEVEL
resetValue | 0
simDoTestBenchWiring | true
simDrivenValue | 0
width | 18
deviceFamily | UNKNOWN
generateLegacySim | false

## Software Assignments
DO_TEST_BENCH_WIRING | 1
DRIVEN_SIM_VALUE | 0x0
HAS_TRI | 1
HAS_OUT | 0
HAS_IN | 0
CAPTURE | 0
BIT_CLEARING_EDGE_REGISTER | 0
BIT_MODIFYING_OUTPUT_REGISTER | 0
DATA_WIDTH | 18
RESET_VALUE | 0x0
EDGE_TYPE | "NONE"
IRQ_TYPE | "NONE"
FREQ | 125000000u

## hsmc_bank3_west

altera_avalon_pio v10.1

pcie0 | pcie_core_clk | hsmc_bank3_west
clk
bar0_Non_Prefetchable
s1

## Parameters
bitClearingEdgeCapReg | false
bitModifyingOutReg | false
captureEdge | false
clockRate | 125000000
direction | Bidir
edgeType | RISING
generateIRQ | false
irqType | LEVEL
resetValue | 0
simDoTestBenchWiring | true
simDrivenValue | 0
width | 18
deviceFamily | UNKNOWN
generateLegacySim | false

## Software Assignments
DO_TEST_BENCH_WIRING | 1
DRIVEN_SIM_VALUE | 0x0
HAS_TRI | 1
HAS_OUT | 0
HAS_IN | 0
CAPTURE | 0
BIT_CLEARING_EDGE_REGISTER | 0
BIT_MODIFYING_OUTPUT_REGISTER | 0
DATA_WIDTH | 18
RESET_VALUE | 0x0
EDGE_TYPE | "NONE"
IRQ_TYPE | "NONE"
FREQ | 125000000u

## hsmc_bank3_east

altera_avalon_pio v10.1

pcie0 | pcie_core_clk | hsmc_bank3_east
clk
bar0_Non_Prefetchable
s1

## Parameters
bitClearingEdgeCapReg | false
bitModifyingOutReg | false
captureEdge | false
clockRate | 125000000
direction | Bidir
edgeType | RISING
generateIRQ | false
irqType | LEVEL
resetValue | 0
simDoTestBenchWiring | true
simDrivenValue | 0
width | 18
deviceFamily | UNKNOWN
generateLegacySim | false

## Software Assignments
DO_TEST_BENCH_WIRING | 1
DRIVEN_SIM_VALUE | 0x0
HAS_TRI | 1
HAS_OUT | 0
HAS_IN | 0
CAPTURE | 0
BIT_CLEARING_EDGE_REGISTER | 0
BIT_MODIFYING_OUTPUT_REGISTER | 0
DATA_WIDTH | 18
RESET_VALUE | 0x0
EDGE_TYPE | "NONE"
IRQ_TYPE | "NONE"
FREQ | 125000000u

## lpcpod_in

altera_avalon_pio v10.1

pcie0 | pcie_core_clk | lpcpod_in
clk
bar0_Non_Prefetchable
s1

## Parameters
bitClearingEdgeCapReg | false
bitModifyingOutReg | false
captureEdge | false
clockRate | 125000000
direction | Input
edgeType | RISING
generateIRQ | false
irqType | LEVEL
resetValue | 0
simDoTestBenchWiring | true
simDrivenValue | 0
width | 8
deviceFamily | UNKNOWN
generateLegacySim | false

## Software Assignments
DO_TEST_BENCH_WIRING | 1
DRIVEN_SIM_VALUE | 0x0
HAS_TRI | 0
HAS_OUT | 0
HAS_IN | 1
CAPTURE | 0
BIT_CLEARING_EDGE_REGISTER | 0
BIT_MODIFYING_OUTPUT_REGISTER | 0
DATA_WIDTH | 8
RESET_VALUE | 0x0
EDGE_TYPE | "NONE"
IRQ_TYPE | "NONE"
FREQ | 125000000u

## hsmc_misc_io

altera_avalon_pio v10.1

pcie0 | pcie_core_clk | hsmc_misc_io
clk
bar0_Non_Prefetchable
s1

## Parameters
bitClearingEdgeCapReg | false
bitModifyingOutReg | false
captureEdge | false
clockRate | 125000000
direction | Bidir
edgeType | RISING
generateIRQ | false
irqType | LEVEL
resetValue | 0
simDoTestBenchWiring | true
simDrivenValue | 0
width | 2
deviceFamily | UNKNOWN
generateLegacySim | false

## Software Assignments
DO_TEST_BENCH_WIRING | 1
DRIVEN_SIM_VALUE | 0x0
HAS_TRI | 1
HAS_OUT | 0
HAS_IN | 0
CAPTURE | 0
BIT_CLEARING_EDGE_REGISTER | 0
BIT_MODIFYING_OUTPUT_REGISTER | 0
DATA_WIDTH | 2
RESET_VALUE | 0x0
EDGE_TYPE | "NONE"
IRQ_TYPE | "NONE"
FREQ | 125000000u

## dma_0

altera_avalon_dma v10.1

pcie0 | pcie_core_clk | dma_0
clk
RxmIrq
irq
bar1_Non_Prefetchable
control_port_slave
|  | write_master | pcie0
|  | Tx_Interface
|  | read_master
|  | Tx_Interface

## Parameters
actualDmaTransactionRegisterWidth | 20
allowByteTransactions | true
allowDoubleWordTransactions | true
allowHalfWordTransactions | true
allowQuadWordTransactions | true
allowWordTransactions | true
bigEndian | false
burstEnable | false
fifoDepth | 32
maxBurstSize | 128
minimumDmaTransactionRegisterWidth | 13
minimumNumberOfByteTransfers | 8191
readAddressMap | <address-map><slave name='pcie0.Tx_Interface' start='0x0' end='0x100000' /></address-map>
readMaximumSlaveSpan | 1048576
readSlaveAddressWidthMax | 20
readSlaveDataWidthMax | 64
useRegistersForFIFO | false
writeAddressMap | <address-map><slave name='pcie0.Tx_Interface' start='0x0' end='0x100000' /></address-map>
writeMaximumSlaveSpan | 1048576
writeSlaveAddressWidthMax | 20
writeSlaveDataWidthMax | 64
deviceFamily | UNKNOWN
generateLegacySim | false

## Software Assignments
LENGTHWIDTH | 13
ALLOW_BYTE_TRANSACTIONS | 1
ALLOW_HW_TRANSACTIONS | 1
ALLOW_WORD_TRANSACTIONS | 1
ALLOW_DOUBLEWORD_TRANSACTIONS | 1
ALLOW_QUADWORD_TRANSACTIONS | 1
MAX_BURST_SIZE | 128

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