# Generation Report - PCI Express Compiler v10.1
Entity Name | altpcie_hip_pipen1b
Ordering Code | IP-PCIE/4
Variation Name | pcie0
Variation HDL | VHDL
Output Directory | D:\MSMST_iotest\fpga
## File Summary The MegaWizard interface is creating the following files in the output directory:
File | Description
--- | ---
pcie0.vhd | This VHDL file instantiates the parameterized PCI Express MegaCore function and the logic required to support the specific PHY selected. It is used for both simulation and compilation in the Quartus II software.
pcie0_core.cmp | This file provides the VHDL component declaration for the MegaCore function variation.
pcie0_core.vhd | This VHDL file configures the PCI Express MegaCore function with the parameters specified. It is used for compilation in the Quartus II software.
pcie0_core.vho | This VHDL file is the parameterized IP Functional Simulation model of the MegaCore function. It is used for simulation.
pcie0_examples | This directory contains PCI Express example design and testbench files.
pcie0_examples | chaining_dma | This directory contains the chaining DMA example design and testbench.
pcie0_examples | chaining_dma | altpcie_dma_descriptor.vhd | This VHDL file contains the altpcie_dma_descriptor entity that retrieves DMA read or write descriptors from the root port memory and stores them in a descriptor FIFO. It is used for simulation and compilation in the Quartus II software.
pcie0_examples | chaining_dma | altpcie_dma_dt.vhd | This VHDL file contains the altpcie_dma_dt entity that arbitrates between PCI Express packets issued by the altpcie_dma_prg_reg, altpcie_read_dma_requester, altpcie_write_dma_requester and altpcie_dma_descriptor entities. It is used for simulation and compilation in the Quartus II software.
pcie0_examples | chaining_dma | altpcie_dma_prg_reg.vhd | This VHDL file implements the descriptor header table registers. It is used for simulation and compilation in the Quartus II software.
pcie0_examples | chaining_dma | altpcie_rc_slave.vhd | This VHDL file contains the altpcie_rc_slave entity that is used by the host software application to retrieve the DMA Performance counter values and directly access the Endpoint memory. It is used for simulation and compilation in the Quartus II software.
pcie0_examples | chaining_dma | altpcie_read_dma_requester.vhd | This VHDL file contains the altpcie_read_dma_requester entity that manages DMA read data transfer from the Root Complex memory to the Endpoint memory. It is used for simulation and compilation in the Quartus II software.
pcie0_examples | chaining_dma | altpcie_write_dma_requester.vhd | This VHDL file contains the altpcie_write_dma_requester entity that manages DMA write data transfer from the Endpoint memory to the Root Complex memory. It is used for simulation and compilation in the Quartus II software.
pcie0_examples | chaining_dma | altpcierd_example_app_chaining.vhd | This VHDL file contains the altpcierd_example_app_chaining entity that is the top level application layer of the chaining DMA example design. It is used for simulation and compilation in the Quartus II software.
pcie0_examples | chaining_dma | init_ram.hex | This memory initialization file is used to initialize the endpoint memory buffer to a ramp. This file is used in simulation.
pcie0_examples | chaining_dma | init_ram.mif | This memory initialization file is used to initialize the endpoint memory buffer to a ramp. This file is used in compilation in the Quartus II software.
pcie0_examples | chaining_dma | testbench | This directory contains files required for simulation of the chaining DMA example design and testbench.
pcie0_examples | chaining_dma | testbench | altpcietb_bfm_driver_chaining.vhd | This VHDL file contains the altpcietb_bfm_driver_chaining entity that drives the testing of the chaining DMA example design. This file is used in simulation.
pcie0_examples | chaining_dma | testbench | init_ram.hex | This memory initialization file is used to initialize the endpoint memory buffer to a ramp. This file is used in simulation.
pcie0_examples | chaining_dma | testbench | init_ram.mif | This memory initialization file is used to initialize the endpoint memory buffer to a ramp. This file is used in compilation in the Quartus II software.
pcie0_examples | chaining_dma | testbench | runtb.bat | This Windows batch file launches the simulation of the chaining DMA example design and testbench.
pcie0_examples | chaining_dma | testbench | runtb.do | This Modelsim simulator TCL script file launches the simulation of the chaining DMA example design and testbench.
pcie0_examples | chaining_dma | testbench | runtb.sh | This shell script file launches the simulation of the chaining DMA example design and testbench.
pcie0_examples | chaining_dma | testbench | sim_filelist | This file is used for simulation of the chaining DMA example design. It contains the list of all the files necessary for compilation in the simulator.
pcie0_examples | chaining_dma | testbench | pcie0_chaining_testbench.vhd | This VHDL file implements the top level of the testbench for the chaining DMA example design.
pcie0_examples | chaining_dma | pcie0_example_chaining_pipen1b.vhd | This VHDL file instantiates the chaining DMA example application layer and the PCI Express MegaCore function variation. It is used for simulation and compilation in the Quartus II software.
pcie0_examples | chaining_dma | pcie0_plus.vhd | This VHDL file instantiates the PCI Express MegaCore function variation and the PCI Express reset circuit. The ALTGX_RECONFIG megafunction is also added to this module when the device family requires transceiver offset cancellation. It is used for simulation and compilation in the Quartus II software.
pcie0_examples | chaining_dma | pcie0_rs_hip.vhd | This VHDL file implements the PCI Express HIP reset circuit. It is used for simulation and compilation in the Quartus II software.
pcie0_examples | chaining_dma | pcie0_example_chaining_top.qpf | This is the Quartus II project file used for compiling the chaining DMA example design.
pcie0_examples | chaining_dma | pcie0_example_chaining_top.qsf | This is the Quartus II settings file used for compiling the chaining DMA example design.
pcie0.sdc | This is the Quartus II TimeQuest Timing Analyzer constraint file.
pcie0_examples | chaining_dma | pcie0_example_chaining_top.tcl | This is a Quartus II TCL script used for applying Classic Timing Analyzer timing constraints to the chaining DMA example design.
pcie0_examples | chaining_dma | pcie0_example_chaining_top.vhd | This VHDL file instantiates the entire chaining DMA example design. It is used for compilation in the Quartus II software.
pcie0_examples | common | This directory contains files required for simulation..
pcie0_examples | common | testbench | This directory contains files required for simulation. These files implement the common BFM and Testbench routines that are described in Chapter 5 of the PCI Express Compiler User Guide.
pcie0_examples | incremental_compile_module | This directory contains files for the incremental compile module. These files are required for simulation and compilation of the simple DMA and chaining DMA example designs
pcie0_examples | incremental_compile_module | altpcierd_icm_fifo.vhd | This VHDL file contains the altpcierd_icm_fifo entity. This is an altera FIFO which is used in the incremental compile module. This file is used for simulation and compilation in the Quartus II software.
pcie0_examples | incremental_compile_module | altpcierd_icm_fifo_lkahd.vhd | This VHDL file contains the altpcierd_icm_fifo_lkahd entity that provides a look-ahead FIFO which is used in the incremental compile module. This file is used for simulation and compilation in the Quartus II software.
pcie0_examples | incremental_compile_module | altpcierd_icm_msibridge.vhd | This VHDL file contains the altpcierd_icm_msibridge entity that implements bridging of the application's msi streaming interface to the core's msi interface . This file is used for simulation and compilation in the Quartus II software.
pcie0_examples | incremental_compile_module | altpcierd_icm_npbypassctl.vhd | This VHDL file contains the altpcierd_icm_npbypassctl entity that implements the controls for bypassing of Non-Posted requests. This file is used for simulation and compilation in the Quartus II software.
pcie0_examples | incremental_compile_module | altpcierd_icm_rx.vhd | This VHDL file contains the altpcierd_icm_rx entity that instantiates an interface FIFO and the altpcierd_icm_rxbridge module. This file is used for simulation and compilation in the Quartus II software.
pcie0_examples | incremental_compile_module | altpcierd_icm_rxbridge.vhd | This VHDL file contains the altpcierd_icm_rxbridge entity that implements bridging of the application's rx streaming interface to the core's rx interface. This file is used for simulation and compilation in the Quartus II software.
pcie0_examples | incremental_compile_module | altpcierd_icm_sideband.vhd | This VHDL file contains the altpcierd_icm_sideband entity that contains boundary registers for the core's sideband signals. This file is used for simulation and compilation in the Quartus II software.
pcie0_examples | incremental_compile_module | altpcierd_icm_top.vhd | This VHDL file contains the altpcierd_icm_top entity. This is the top level module for the incremental compile module. It contains the altpcierd_icm_rx, altpcierd_tx, altpcierd_sideband modules. This file is used for simulation and compilation in the Quartus II software.
pcie0_examples | incremental_compile_module | altpcierd_icm_tx.vhd | This VHDL file contains the altpcierd_icm_tx entity that instantiates an interface FIFO, the altpcierd_msi_bridge and altpcierd_icm_txbridge_withbypass modules. This file is used for simulation and compilation in the Quartus II software.
pcie0_examples | incremental_compile_module | altpcierd_icm_tx_pktordering.vhd | This VHDL file contains the altpcierd_icm_tx_pktordering entity that implements packet reordering for bypassing of non-posted requests (npbypass). It contains the npbypass Fifos and the altpcierd_npbypassctl module. This file is used for simulation and compilation in the Quartus II software.
pcie0_examples | incremental_compile_module | altpcierd_icm_txbridge.vhd | This VHDL file contains the altpcierd_icm_txbridge entity that implements bridging of the application's tx streaming interface to the core's tx interface. This file is used for simulation and compilation in the Quartus II software.
pcie0_examples | incremental_compile_module | altpcierd_icm_txbridge_withbypass.vhd | This VHDL file contains the altpcierd_icm_txbridge_withbypass entity which instantiates the altpcierd_icm_tx_pktordering and altpcierd_icm_txbridge modules. This file is used for simulation and compilation in the Quartus II software.
pcie0_examples | incremental_compile_module | pcie0_icm.vhd | This VHDL file contains the VAR_icm entity that instantiates the altpcierd_icm_top and the VAR modules. This file is used for simulation and compilation in the Quartus II software.
pcie0_serdes.vhd | Variation file from the ALT2GXB Megafunction.This file contains the on-chip transceiver settings for PCI Express.
pcie0.ppx | This XML file is a Pin Planner support file that Pin Planner automatically uses. This file must remain in the same directory as the pcie0.ppf file.
pcie0.ppf | This XML file describes the MegaCore pin attributes to the Quartus II Pin Planner. MegaCore pin attributes include pin direction, location, I/O standard assignments, and drive strength. If you launch the MegaWizard outside of the Pin Planner application, you must explicitly load this file to use Pin Planner.
pcie0.qip | Contains Quartus II project information for your MegaCore function variation.
pcie0.html | The MegaCore function report file.
## MegaCore Function Variation File Ports
Name | Direction | Width
--- | --- | ---
AvlClk_i | INPUT | 1
CraAddress_i | INPUT | 12
CraByteEnable_i | INPUT | 4
CraChipSelect_i | INPUT | 1
CraRead | INPUT | 1
CraWrite | INPUT | 1
CraWriteData_i | INPUT | 32
Rstn_i | INPUT | 1
RxmIrqNum_i | INPUT | 6
RxmIrq_i | INPUT | 1
RxmReadDataValid_i | INPUT | 1
RxmReadData_i | INPUT | 64
RxmWaitRequest_i | INPUT | 1
TxsAddress_i | INPUT | 17
TxsBurstCount_i | INPUT | 10
TxsByteEnable_i | INPUT | 8
TxsChipSelect_i | INPUT | 1
TxsRead_i | INPUT | 1
TxsWriteData_i | INPUT | 64
TxsWrite_i | INPUT | 1
aer_msi_num | INPUT | 5
app_int_sts | INPUT | 1
app_msi_num | INPUT | 5
app_msi_req | INPUT | 1
app_msi_tc | INPUT | 3
core_clk_in | INPUT | 1
cpl_err | INPUT | 7
cpl_pending | INPUT | 1
crst | INPUT | 1
hpg_ctrler | INPUT | 5
lmi_addr | INPUT | 12
lmi_din | INPUT | 32
lmi_rden | INPUT | 1
lmi_wren | INPUT | 1
npor | INPUT | 1
pclk_central | INPUT | 1
pclk_ch0 | INPUT | 1
pex_msi_num | INPUT | 5
pld_clk | INPUT | 1
pll_fixed_clk | INPUT | 1
pm_auxpwr | INPUT | 1
pm_data | INPUT | 10
pm_event | INPUT | 1
pme_to_cr | INPUT | 1
rc_areset | INPUT | 1
rc_inclk_eq_125mhz | INPUT | 1
rc_pll_locked | INPUT | 1
rc_rx_pll_locked_one | INPUT | 1
rx_st_mask0 | INPUT | 1
rx_st_ready0 | INPUT | 1
srst | INPUT | 1
test_in | INPUT | 40
tx_st_data0 | INPUT | 64
tx_st_data0_p1 | INPUT | 64
tx_st_eop0 | INPUT | 1
tx_st_eop0_p1 | INPUT | 1
tx_st_err0 | INPUT | 1
tx_st_sop0 | INPUT | 1
tx_st_sop0_p1 | INPUT | 1
tx_st_valid0 | INPUT | 1
phystatus0_ext | INPUT | 1
rxdata0_ext | INPUT | 8
rxdatak0_ext | INPUT | 1
rxelecidle0_ext | INPUT | 1
rxstatus0_ext | INPUT | 3
rxvalid0_ext | INPUT | 1
CraIrq_o | OUTPUT | 1
CraReadData_o | OUTPUT | 32
CraWaitRequest_o | OUTPUT | 1
RxmAddress_o | OUTPUT | 32
RxmBurstCount_o | OUTPUT | 10
RxmByteEnable_o | OUTPUT | 8
RxmRead_o | OUTPUT | 1
RxmWriteData_o | OUTPUT | 64
RxmWrite_o | OUTPUT | 1
TxsReadDataValid_o | OUTPUT | 1
TxsReadData_o | OUTPUT | 64
TxsWaitRequest_o | OUTPUT | 1
app_int_ack | OUTPUT | 1
app_msi_ack | OUTPUT | 1
avs_pcie_reconfig_readdata | OUTPUT | 16
avs_pcie_reconfig_readdatavalid | OUTPUT | 1
avs_pcie_reconfig_waitrequest | OUTPUT | 1
core_clk_out | OUTPUT | 1
derr_cor_ext_rcv0 | OUTPUT | 1
derr_cor_ext_rpl | OUTPUT | 1
derr_rpl | OUTPUT | 1
dl_ltssm | OUTPUT | 5
dlup_exit | OUTPUT | 1
eidle_infer_sel | OUTPUT | 24
ev_128ns | OUTPUT | 1
ev_1us | OUTPUT | 1
hip_extraclkout | OUTPUT | 2
hotrst_exit | OUTPUT | 1
int_status | OUTPUT | 4
l2_exit | OUTPUT | 1
lane_act | OUTPUT | 4
lmi_ack | OUTPUT | 1
lmi_dout | OUTPUT | 32
npd_alloc_1cred_vc0 | OUTPUT | 1
npd_cred_vio_vc0 | OUTPUT | 1
nph_alloc_1cred_vc0 | OUTPUT | 1
nph_cred_vio_vc0 | OUTPUT | 1
pme_to_sr | OUTPUT | 1
r2c_err0 | OUTPUT | 1
rate_ext | OUTPUT | 1
rc_gxb_powerdown | OUTPUT | 1
rc_rx_analogreset | OUTPUT | 1
rc_rx_digitalreset | OUTPUT | 1
rc_tx_digitalreset | OUTPUT | 1
reset_status | OUTPUT | 1
rx_fifo_empty0 | OUTPUT | 1
rx_fifo_full0 | OUTPUT | 1
rx_st_bardec0 | OUTPUT | 8
rx_st_be0 | OUTPUT | 8
rx_st_be0_p1 | OUTPUT | 8
rx_st_data0 | OUTPUT | 64
rx_st_data0_p1 | OUTPUT | 64
rx_st_eop0 | OUTPUT | 1
rx_st_eop0_p1 | OUTPUT | 1
rx_st_err0 | OUTPUT | 1
rx_st_sop0 | OUTPUT | 1
rx_st_sop0_p1 | OUTPUT | 1
rx_st_valid0 | OUTPUT | 1
serr_out | OUTPUT | 1
suc_spd_neg | OUTPUT | 1
swdn_wake | OUTPUT | 1
swup_hotrst | OUTPUT | 1
test_out | OUTPUT | 64
tl_cfg_add | OUTPUT | 4
tl_cfg_ctl | OUTPUT | 32
tl_cfg_ctl_wr | OUTPUT | 1
tl_cfg_sts | OUTPUT | 53
tl_cfg_sts_wr | OUTPUT | 1
tx_cred0 | OUTPUT | 36
tx_deemph | OUTPUT | 8
tx_fifo_empty0 | OUTPUT | 1
tx_fifo_full0 | OUTPUT | 1
tx_fifo_rdptr0 | OUTPUT | 4
tx_fifo_wrptr0 | OUTPUT | 4
tx_margin | OUTPUT | 24
tx_st_ready0 | OUTPUT | 1
use_pcie_reconfig | OUTPUT | 1
wake_oen | OUTPUT | 1
powerdown0_ext | OUTPUT | 2
rxpolarity0_ext | OUTPUT | 1
txcompl0_ext | OUTPUT | 1
txdata0_ext | OUTPUT | 8
txdatak0_ext | OUTPUT | 1
txdetectrx0_ext | OUTPUT | 1
txelecidle0_ext | OUTPUT | 1