SYSTEM msmst_test
{
   System_Wizard_Version = "10.11";
   System_Wizard_Build = "197";
   Builder_Application = "sopc_builder_ca";
   WIZARD_SCRIPT_ARGUMENTS 
   {
      hdl_language = "vhdl";
      device_family = "ARRIAII";
      device_family_id = "ARRIAII";
      generate_sdk = "0";
      do_build_sim = "0";
      hardcopy_compatible = "0";
      CLOCKS 
      {
         CLOCK pcie0_pcie_core_clk
         {
            frequency = "125000000";
            source = "";
            Is_Clock_Source = "1";
            display_name = "pcie_core_clk from pcie0";
            pipeline = "0";
            clock_module_connection_point_for_c2h = "pcie0.pcie_core_clk";
         }
         CLOCK pcie0_pcie_core_clk_out
         {
            frequency = "125000000";
            source = "pcie0_pcie_core_clk";
            Is_Clock_Source = "0";
            display_name = "pcie0_pcie_core_clk_out";
         }
      }
      clock_freq = "125000000";
      clock_freq = "125000000";
      board_class = "";
      view_master_columns = "1";
      view_master_priorities = "0";
      generate_hdl = "";
      bustype_column_width = "0";
      clock_column_width = "80";
      name_column_width = "75";
      desc_column_width = "75";
      base_column_width = "75";
      end_column_width = "75";
      do_log_history = "0";
   }
   MODULE pcie0
   {
      PORT_WIRING 
      {
         PORT pcie_core_clk
         {
            type = "out_clk";
            width = "1";
            direction = "output";
            Is_Enabled = "1";
         }
         PORT cal_blk_clk
         {
            type = "clk";
            width = "1";
            direction = "input";
            Is_Enabled = "1";
         }
         PORT pcie_rstn
         {
            type = "export";
            width = "1";
            direction = "input";
            Is_Enabled = "1";
            _exclusive_name = "pcie_rstn_pcie0";
         }
         PORT phystatus_ext
         {
            type = "export";
            width = "1";
            direction = "input";
            Is_Enabled = "1";
            _exclusive_name = "phystatus_ext_pcie0";
         }
         PORT rx_in0
         {
            type = "export";
            width = "1";
            direction = "input";
            Is_Enabled = "1";
            _exclusive_name = "rx_in0_pcie0";
         }
         PORT refclk
         {
            type = "export";
            width = "1";
            direction = "input";
            Is_Enabled = "1";
            _exclusive_name = "refclk_pcie0";
         }
         PORT rxdata0_ext
         {
            type = "export";
            width = "8";
            direction = "input";
            Is_Enabled = "1";
            _exclusive_name = "rxdata0_ext_pcie0";
         }
         PORT reconfig_clk
         {
            type = "export";
            width = "1";
            direction = "input";
            Is_Enabled = "1";
            _exclusive_name = "reconfig_clk_pcie0";
         }
         PORT reconfig_togxb
         {
            type = "export";
            width = "4";
            direction = "input";
            Is_Enabled = "1";
            _exclusive_name = "reconfig_togxb_pcie0";
         }
         PORT gxb_powerdown
         {
            type = "export";
            width = "1";
            direction = "input";
            Is_Enabled = "1";
            _exclusive_name = "gxb_powerdown_pcie0";
         }
         PORT pll_powerdown
         {
            type = "export";
            width = "1";
            direction = "input";
            Is_Enabled = "1";
            _exclusive_name = "pll_powerdown_pcie0";
         }
         PORT fixedclk_serdes
         {
            type = "export";
            width = "1";
            direction = "input";
            Is_Enabled = "1";
            _exclusive_name = "fixedclk_serdes_pcie0";
         }
         PORT busy_altgxb_reconfig
         {
            type = "export";
            width = "1";
            direction = "input";
            Is_Enabled = "1";
            _exclusive_name = "busy_altgxb_reconfig_pcie0";
         }
         PORT rxdatak0_ext
         {
            type = "export";
            width = "1";
            direction = "input";
            Is_Enabled = "1";
            _exclusive_name = "rxdatak0_ext_pcie0";
         }
         PORT rxelecidle0_ext
         {
            type = "export";
            width = "1";
            direction = "input";
            Is_Enabled = "1";
            _exclusive_name = "rxelecidle0_ext_pcie0";
         }
         PORT rxstatus0_ext
         {
            type = "export";
            width = "3";
            direction = "input";
            Is_Enabled = "1";
            _exclusive_name = "rxstatus0_ext_pcie0";
         }
         PORT rxvalid0_ext
         {
            type = "export";
            width = "1";
            direction = "input";
            Is_Enabled = "1";
            _exclusive_name = "rxvalid0_ext_pcie0";
         }
         PORT test_in
         {
            type = "export";
            width = "40";
            direction = "input";
            Is_Enabled = "1";
            _exclusive_name = "test_in_pcie0";
         }
         PORT pipe_mode
         {
            type = "export";
            width = "1";
            direction = "input";
            Is_Enabled = "1";
            _exclusive_name = "pipe_mode_pcie0";
         }
         PORT clk125_out
         {
            type = "export";
            width = "1";
            direction = "output";
            Is_Enabled = "1";
            _exclusive_name = "clk125_out_pcie0";
         }
         PORT tx_out0
         {
            type = "export";
            width = "1";
            direction = "output";
            Is_Enabled = "1";
            _exclusive_name = "tx_out0_pcie0";
         }
         PORT powerdown_ext
         {
            type = "export";
            width = "2";
            direction = "output";
            Is_Enabled = "1";
            _exclusive_name = "powerdown_ext_pcie0";
         }
         PORT rxpolarity0_ext
         {
            type = "export";
            width = "1";
            direction = "output";
            Is_Enabled = "1";
            _exclusive_name = "rxpolarity0_ext_pcie0";
         }
         PORT reconfig_fromgxb
         {
            type = "export";
            width = "17";
            direction = "output";
            Is_Enabled = "1";
            _exclusive_name = "reconfig_fromgxb_pcie0";
         }
         PORT clk250_out
         {
            type = "export";
            width = "1";
            direction = "output";
            Is_Enabled = "1";
            _exclusive_name = "clk250_out_pcie0";
         }
         PORT clk500_out
         {
            type = "export";
            width = "1";
            direction = "output";
            Is_Enabled = "1";
            _exclusive_name = "clk500_out_pcie0";
         }
         PORT rate_ext
         {
            type = "export";
            width = "1";
            direction = "output";
            Is_Enabled = "1";
            _exclusive_name = "rate_ext_pcie0";
         }
         PORT txcompl0_ext
         {
            type = "export";
            width = "1";
            direction = "output";
            Is_Enabled = "1";
            _exclusive_name = "txcompl0_ext_pcie0";
         }
         PORT txdata0_ext
         {
            type = "export";
            width = "8";
            direction = "output";
            Is_Enabled = "1";
            _exclusive_name = "txdata0_ext_pcie0";
         }
         PORT txdatak0_ext
         {
            type = "export";
            width = "1";
            direction = "output";
            Is_Enabled = "1";
            _exclusive_name = "txdatak0_ext_pcie0";
         }
         PORT txdetectrx_ext
         {
            type = "export";
            width = "1";
            direction = "output";
            Is_Enabled = "1";
            _exclusive_name = "txdetectrx_ext_pcie0";
         }
         PORT txelecidle0_ext
         {
            type = "export";
            width = "1";
            direction = "output";
            Is_Enabled = "1";
            _exclusive_name = "txelecidle0_ext_pcie0";
         }
      }
      MASTER bar0_Non_Prefetchable
      {
         PORT_WIRING 
         {
            PORT AvlClk_i
            {
               type = "clk";
               width = "1";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT reset_n
            {
               type = "reset_n";
               width = "1";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT RxmIrqNum_i
            {
               type = "irqnumber";
               width = "6";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT RxmIrq_i
            {
               type = "irq";
               width = "1";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT RxmAddress_o
            {
               type = "address";
               width = "32";
               direction = "output";
               Is_Enabled = "1";
            }
            PORT RxmBurstCount_o
            {
               type = "burstcount";
               width = "10";
               direction = "output";
               Is_Enabled = "1";
            }
            PORT RxmByteEnable_o
            {
               type = "byteenable";
               width = "8";
               direction = "output";
               Is_Enabled = "1";
            }
            PORT RxmRead_o
            {
               type = "read";
               width = "1";
               direction = "output";
               Is_Enabled = "1";
            }
            PORT RxmReadData_i
            {
               type = "readdata";
               width = "64";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT RxmReadDataValid_i
            {
               type = "readdatavalid";
               width = "1";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT RxmWaitRequest_i
            {
               type = "waitrequest";
               width = "1";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT RxmWrite_o
            {
               type = "write";
               width = "1";
               direction = "output";
               Is_Enabled = "1";
            }
            PORT RxmWriteData_o
            {
               type = "writedata";
               width = "64";
               direction = "output";
               Is_Enabled = "1";
            }
            PORT RxmResetRequest_o
            {
               type = "resetrequest";
               width = "1";
               direction = "output";
               Is_Enabled = "1";
            }
         }
         SYSTEM_BUILDER_INFO 
         {
            Has_IRQ = "1";
            Irq_Scheme = "priority_encoded";
            Bus_Type = "avalon";
            Is_Asynchronous = "0";
            DBS_Big_Endian = "0";
            Adapts_To = "";
            Do_Stream_Reads = "0";
            Do_Stream_Writes = "0";
            Max_Address_Width = "32";
            Data_Width = "64";
            Address_Width = "32";
            Maximum_Burst_Size = "512";
            Register_Incoming_Signals = "0";
            Register_Outgoing_Signals = "0";
            Interleave_Bursts = "0";
            Linewrap_Bursts = "0";
            Burst_On_Burst_Boundaries_Only = "0";
            Always_Burst_Max_Burst = "0";
            Is_Big_Endian = "0";
            Is_Enabled = "0";
            Clock_Source = "pcie0_pcie_core_clk_out";
            Has_Clock = "1";
         }
         MEMORY_MAP 
         {
            Entry gpio_west/s1
            {
               address = "0x80004100";
               span = "0x00000020";
               is_bridge = "0";
            }
            Entry gpio_east/s1
            {
               address = "0x80004180";
               span = "0x00000020";
               is_bridge = "0";
            }
            Entry hsmc_misc_in/s1
            {
               address = "0x80004200";
               span = "0x00000020";
               is_bridge = "0";
            }
            Entry hsmc_misc_out/s1
            {
               address = "0x80004280";
               span = "0x00000020";
               is_bridge = "0";
            }
            Entry hsmc_misc_io/s1
            {
               address = "0x80004300";
               span = "0x00000020";
               is_bridge = "0";
            }
            Entry hsmc_bank2_west/s1
            {
               address = "0x80004380";
               span = "0x00000020";
               is_bridge = "0";
            }
            Entry hsmc_bank2_east/s1
            {
               address = "0x80004400";
               span = "0x00000020";
               is_bridge = "0";
            }
            Entry hsmc_bank3_west/s1
            {
               address = "0x80004480";
               span = "0x00000020";
               is_bridge = "0";
            }
            Entry hsmc_bank3_east/s1
            {
               address = "0x80004500";
               span = "0x00000020";
               is_bridge = "0";
            }
            Entry lpcpod_in/s1
            {
               address = "0x80004580";
               span = "0x00000020";
               is_bridge = "0";
            }
         }
      }
      SLAVE Tx_Interface
      {
         SYSTEM_BUILDER_INFO 
         {
            Bus_Type = "avalon";
            Read_Wait_States = "peripheral_controlled";
            Write_Wait_States = "peripheral_controlled";
            Hold_Time = "0cycles";
            Setup_Time = "0cycles";
            Is_Printable_Device = "0";
            Address_Alignment = "dynamic";
            Well_Behaved_Waitrequest = "0";
            Is_Nonvolatile_Storage = "0";
            Address_Span = "1048576";
            Read_Latency = "0";
            Is_Memory_Device = "0";
            Maximum_Pending_Read_Transactions = "32";
            Minimum_Uninterrupted_Run_Length = "1";
            Accepts_Internal_Connections = "1";
            Write_Latency = "0";
            Is_Flash = "0";
            Data_Width = "64";
            Address_Width = "17";
            Maximum_Burst_Size = "512";
            Register_Incoming_Signals = "0";
            Register_Outgoing_Signals = "0";
            Interleave_Bursts = "0";
            Linewrap_Bursts = "0";
            Burst_On_Burst_Boundaries_Only = "0";
            Always_Burst_Max_Burst = "0";
            Is_Big_Endian = "0";
            Is_Enabled = "1";
            Clock_Source = "pcie0_pcie_core_clk_out";
            Has_Clock = "1";
            MASTERED_BY dma_0/write_master
            {
               priority = "1";
               Offset_Address = "0x00000000";
            }
            MASTERED_BY dma_0/read_master
            {
               priority = "1";
               Offset_Address = "0x00000000";
            }
            Base_Address = "0x00000000";
            Address_Group = "0";
         }
         PORT_WIRING 
         {
            PORT TxsChipSelect_i
            {
               type = "chipselect";
               width = "1";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT TxsByteEnable_i
            {
               type = "byteenable";
               width = "8";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT TxsReadData_o
            {
               type = "readdata";
               width = "64";
               direction = "output";
               Is_Enabled = "1";
            }
            PORT TxsWriteData_i
            {
               type = "writedata";
               width = "64";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT TxsAddress_i
            {
               type = "address";
               width = "17";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT TxsRead_i
            {
               type = "read";
               width = "1";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT TxsWrite_i
            {
               type = "write";
               width = "1";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT TxsReadDataValid_o
            {
               type = "readdatavalid";
               width = "1";
               direction = "output";
               Is_Enabled = "1";
            }
            PORT TxsWaitRequest_o
            {
               type = "waitrequest";
               width = "1";
               direction = "output";
               Is_Enabled = "1";
            }
            PORT TxsBurstCount_i
            {
               type = "burstcount";
               width = "10";
               direction = "input";
               Is_Enabled = "1";
            }
         }
      }
      SLAVE Control_Register_Access
      {
         SYSTEM_BUILDER_INFO 
         {
            Has_IRQ = "1";
            Bus_Type = "avalon";
            Read_Wait_States = "peripheral_controlled";
            Write_Wait_States = "peripheral_controlled";
            Hold_Time = "0cycles";
            Setup_Time = "0cycles";
            Is_Printable_Device = "0";
            Address_Alignment = "dynamic";
            Well_Behaved_Waitrequest = "0";
            Is_Nonvolatile_Storage = "0";
            Address_Span = "16384";
            Read_Latency = "0";
            Is_Memory_Device = "0";
            Maximum_Pending_Read_Transactions = "0";
            Minimum_Uninterrupted_Run_Length = "1";
            Accepts_Internal_Connections = "1";
            Write_Latency = "0";
            Is_Flash = "0";
            Data_Width = "32";
            Address_Width = "12";
            Maximum_Burst_Size = "1";
            Register_Incoming_Signals = "0";
            Register_Outgoing_Signals = "0";
            Interleave_Bursts = "0";
            Linewrap_Bursts = "0";
            Burst_On_Burst_Boundaries_Only = "0";
            Always_Burst_Max_Burst = "0";
            Is_Big_Endian = "0";
            Is_Enabled = "1";
            Clock_Source = "pcie0_pcie_core_clk_out";
            Has_Clock = "1";
            MASTERED_BY pcie0/Rx_Interface
            {
               priority = "1";
               Offset_Address = "0x80000000";
            }
            Base_Address = "0x80000000";
            Address_Group = "1";
            IRQ_MASTER pcie0/Rx_Interface
            {
               IRQ_Number = "NC";
            }
         }
         PORT_WIRING 
         {
            PORT CraIrq_o
            {
               type = "irq";
               width = "1";
               direction = "output";
               Is_Enabled = "1";
            }
            PORT CraChipSelect_i
            {
               type = "chipselect";
               width = "1";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT CraAddress_i
            {
               type = "address";
               width = "12";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT CraByteEnable_i
            {
               type = "byteenable";
               width = "4";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT CraRead
            {
               type = "read";
               width = "1";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT CraReadData_o
            {
               type = "readdata";
               width = "32";
               direction = "output";
               Is_Enabled = "1";
            }
            PORT CraWrite
            {
               type = "write";
               width = "1";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT CraWriteData_i
            {
               type = "writedata";
               width = "32";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT CraWaitRequest_o
            {
               type = "waitrequest";
               width = "1";
               direction = "output";
               Is_Enabled = "1";
            }
         }
      }
      MASTER bar1_Non_Prefetchable
      {
         SYSTEM_BUILDER_INFO 
         {
            Bus_Type = "avalon";
            Is_Asynchronous = "0";
            DBS_Big_Endian = "0";
            Adapts_To = "";
            Do_Stream_Reads = "0";
            Do_Stream_Writes = "0";
            Max_Address_Width = "32";
            Data_Width = "64";
            Address_Width = "32";
            Maximum_Burst_Size = "512";
            Register_Incoming_Signals = "0";
            Register_Outgoing_Signals = "0";
            Interleave_Bursts = "0";
            Linewrap_Bursts = "0";
            Burst_On_Burst_Boundaries_Only = "0";
            Always_Burst_Max_Burst = "0";
            Is_Big_Endian = "0";
            Is_Enabled = "0";
            Clock_Source = "pcie0_pcie_core_clk_out";
            Has_Clock = "1";
         }
         PORT_WIRING 
         {
            PORT RxmAddress_o
            {
               type = "address";
               width = "32";
               direction = "output";
               Is_Enabled = "1";
            }
            PORT RxmBurstCount_o
            {
               type = "burstcount";
               width = "10";
               direction = "output";
               Is_Enabled = "1";
            }
            PORT RxmByteEnable_o
            {
               type = "byteenable";
               width = "8";
               direction = "output";
               Is_Enabled = "1";
            }
            PORT RxmRead_o
            {
               type = "read";
               width = "1";
               direction = "output";
               Is_Enabled = "1";
            }
            PORT RxmReadData_i
            {
               type = "readdata";
               width = "64";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT RxmReadDataValid_i
            {
               type = "readdatavalid";
               width = "1";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT RxmWaitRequest_i
            {
               type = "waitrequest";
               width = "1";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT RxmWrite_o
            {
               type = "write";
               width = "1";
               direction = "output";
               Is_Enabled = "1";
            }
            PORT RxmWriteData_o
            {
               type = "writedata";
               width = "64";
               direction = "output";
               Is_Enabled = "1";
            }
            PORT RxmResetRequest_o
            {
               type = "resetrequest";
               width = "1";
               direction = "output";
               Is_Enabled = "1";
            }
         }
         MEMORY_MAP 
         {
            Entry pcie0/Control_Register_Access
            {
               address = "0x80000000";
               span = "0x00004000";
               is_bridge = "0";
            }
            Entry dma_0/control_port_slave
            {
               address = "0x80004000";
               span = "0x00000040";
               is_bridge = "0";
            }
         }
      }
      SYSTEM_BUILDER_INFO 
      {
         Do_Not_Generate = "1";
         Instantiate_In_System_Module = "1";
         Is_Enabled = "1";
         Clock_Source = "pcie0_pcie_core_clk_out";
         Has_Clock = "1";
         Pins_Assigned_Automatically = "1";
         View 
         {
            MESSAGES 
            {
            }
         }
      }
      SIMULATION 
      {
         Module_Name = "pcie0_testbench";
         PORT_WIRING 
         {
            preserve = "1";
            PORT pcie_rstn
            {
               direction = "output";
               width = "1";
               __exclusive_name = "pcie_rstn_pcie0";
               Is_Enabled = "1";
            }
            PORT phystatus_ext
            {
               direction = "output";
               width = "1";
               __exclusive_name = "phystatus_ext_pcie0";
               Is_Enabled = "1";
            }
            PORT rx_in0
            {
               direction = "output";
               width = "1";
               __exclusive_name = "rx_in0_pcie0";
               Is_Enabled = "1";
            }
            PORT refclk
            {
               direction = "output";
               width = "1";
               __exclusive_name = "refclk_pcie0";
               Is_Enabled = "1";
            }
            PORT rxdata0_ext
            {
               direction = "output";
               width = "8";
               __exclusive_name = "rxdata0_ext_pcie0";
               Is_Enabled = "1";
            }
            PORT reconfig_clk
            {
               direction = "output";
               width = "1";
               __exclusive_name = "reconfig_clk_pcie0";
               Is_Enabled = "1";
            }
            PORT reconfig_togxb
            {
               direction = "output";
               width = "4";
               __exclusive_name = "reconfig_togxb_pcie0";
               Is_Enabled = "1";
            }
            PORT gxb_powerdown
            {
               direction = "output";
               width = "1";
               __exclusive_name = "gxb_powerdown_pcie0";
               Is_Enabled = "1";
            }
            PORT pll_powerdown
            {
               direction = "output";
               width = "1";
               __exclusive_name = "pll_powerdown_pcie0";
               Is_Enabled = "1";
            }
            PORT fixedclk_serdes
            {
               direction = "output";
               width = "1";
               __exclusive_name = "fixedclk_serdes_pcie0";
               Is_Enabled = "1";
            }
            PORT busy_altgxb_reconfig
            {
               direction = "output";
               width = "1";
               __exclusive_name = "busy_altgxb_reconfig_pcie0";
               Is_Enabled = "1";
            }
            PORT rxdatak0_ext
            {
               direction = "output";
               width = "1";
               __exclusive_name = "rxdatak0_ext_pcie0";
               Is_Enabled = "1";
            }
            PORT rxelecidle0_ext
            {
               direction = "output";
               width = "1";
               __exclusive_name = "rxelecidle0_ext_pcie0";
               Is_Enabled = "1";
            }
            PORT rxstatus0_ext
            {
               direction = "output";
               width = "3";
               __exclusive_name = "rxstatus0_ext_pcie0";
               Is_Enabled = "1";
            }
            PORT rxvalid0_ext
            {
               direction = "output";
               width = "1";
               __exclusive_name = "rxvalid0_ext_pcie0";
               Is_Enabled = "1";
            }
            PORT test_in
            {
               direction = "output";
               width = "40";
               __exclusive_name = "test_in_pcie0";
               Is_Enabled = "1";
            }
            PORT pipe_mode
            {
               direction = "output";
               width = "1";
               __exclusive_name = "pipe_mode_pcie0";
               Is_Enabled = "1";
            }
            PORT clk125_out
            {
               direction = "input";
               width = "1";
               __exclusive_name = "clk125_out_pcie0";
               Is_Enabled = "1";
            }
            PORT tx_out0
            {
               direction = "input";
               width = "1";
               __exclusive_name = "tx_out0_pcie0";
               Is_Enabled = "1";
            }
            PORT powerdown_ext
            {
               direction = "input";
               width = "2";
               __exclusive_name = "powerdown_ext_pcie0";
               Is_Enabled = "1";
            }
            PORT rxpolarity0_ext
            {
               direction = "input";
               width = "1";
               __exclusive_name = "rxpolarity0_ext_pcie0";
               Is_Enabled = "1";
            }
            PORT reconfig_fromgxb
            {
               direction = "input";
               width = "17";
               __exclusive_name = "reconfig_fromgxb_pcie0";
               Is_Enabled = "1";
            }
            PORT clk250_out
            {
               direction = "input";
               width = "1";
               __exclusive_name = "clk250_out_pcie0";
               Is_Enabled = "1";
            }
            PORT clk500_out
            {
               direction = "input";
               width = "1";
               __exclusive_name = "clk500_out_pcie0";
               Is_Enabled = "1";
            }
            PORT rate_ext
            {
               direction = "input";
               width = "1";
               __exclusive_name = "rate_ext_pcie0";
               Is_Enabled = "1";
            }
            PORT txcompl0_ext
            {
               direction = "input";
               width = "1";
               __exclusive_name = "txcompl0_ext_pcie0";
               Is_Enabled = "1";
            }
            PORT txdata0_ext
            {
               direction = "input";
               width = "8";
               __exclusive_name = "txdata0_ext_pcie0";
               Is_Enabled = "1";
            }
            PORT txdatak0_ext
            {
               direction = "input";
               width = "1";
               __exclusive_name = "txdatak0_ext_pcie0";
               Is_Enabled = "1";
            }
            PORT txdetectrx_ext
            {
               direction = "input";
               width = "1";
               __exclusive_name = "txdetectrx_ext_pcie0";
               Is_Enabled = "1";
            }
            PORT txelecidle0_ext
            {
               direction = "input";
               width = "1";
               __exclusive_name = "txelecidle0_ext_pcie0";
               Is_Enabled = "1";
            }
         }
      }
      HDL_INFO 
      {
         Synthesis_Only_Files = "__PROJECT__DIRECTORY__/pcie0.vhd";
         Simulation_HDL_Files = "w:/altera/10.1/quartus/eda/sim_lib/stratixgx_mf.vhd,w:/altera/10.1/quartus/eda/sim_lib/stratixgx_mf_components.vhd,w:/altera/10.1/quartus/eda/sim_lib/stratixiigx_hssi_components.vhd,w:/altera/10.1/quartus/eda/sim_lib/stratixiigx_hssi_atoms.vhd,w:/altera/10.1/quartus/eda/sim_lib/altera_primitives_components.vhd,w:/altera/10.1/quartus/eda/sim_lib/altera_primitives.vhd,w:/altera/10.1/quartus/eda/sim_lib/stratixiv_atoms.vhd,w:/altera/10.1/quartus/eda/sim_lib/stratixiv_components.vhd,w:/altera/10.1/quartus/eda/sim_lib/stratixiv_hssi_components.vhd,w:/altera/10.1/quartus/eda/sim_lib/stratixiv_hssi_atoms.vhd,w:/altera/10.1/quartus/eda/sim_lib/stratixiv_pcie_hip_components.vhd,w:/altera/10.1/quartus/eda/sim_lib/stratixiv_pcie_hip_atoms.vhd,w:/altera/10.1/quartus/eda/sim_lib/cycloneiv_atoms.vhd,w:/altera/10.1/quartus/eda/sim_lib/cycloneiv_components.vhd,w:/altera/10.1/quartus/eda/sim_lib/cycloneiv_hssi_components.vhd,w:/altera/10.1/quartus/eda/sim_lib/cycloneiv_hssi_atoms.vhd,w:/altera/10.1/quartus/eda/sim_lib/cycloneiv_pcie_hip_components.vhd,w:/altera/10.1/quartus/eda/sim_lib/cycloneiv_pcie_hip_atoms.vhd,w:/altera/10.1/quartus/eda/sim_lib/hardcopyiv_atoms.vhd,w:/altera/10.1/quartus/eda/sim_lib/hardcopyiv_components.vhd,w:/altera/10.1/quartus/eda/sim_lib/hardcopyiv_hssi_components.vhd,w:/altera/10.1/quartus/eda/sim_lib/hardcopyiv_hssi_atoms.vhd,w:/altera/10.1/quartus/eda/sim_lib/hardcopyiv_pcie_hip_components.vhd,w:/altera/10.1/quartus/eda/sim_lib/hardcopyiv_pcie_hip_atoms.vhd,w:/altera/10.1/quartus/eda/sim_lib/arriaii_atoms.vhd,w:/altera/10.1/quartus/eda/sim_lib/arriaii_components.vhd,w:/altera/10.1/quartus/eda/sim_lib/arriaii_hssi_components.vhd,w:/altera/10.1/quartus/eda/sim_lib/arriaii_hssi_atoms.vhd,w:/altera/10.1/quartus/eda/sim_lib/arriaii_pcie_hip_components.vhd,w:/altera/10.1/quartus/eda/sim_lib/arriaii_pcie_hip_atoms.vhd,../pcie0_core.vho,../pcie0.vhd,../pcie0_serdes.vhd,../pcie0_examples/common/testbench/altpcie_rs_serdes.vhd,../pcie0_examples/common/testbench/altpcie_phasefifo.vhd,../pcie0_examples/common/testbench/altpcie_pll_125_250.vhd,../pcie0_examples/common/testbench/altpcie_pll_100_125.vhd,../pcie0_examples/common/testbench/altpcie_pll_100_250.vhd,../pcie0_examples/common/testbench/altpcie_pll_phy0.vhd,../pcie0_examples/common/testbench/altpcie_pll_phy1_62p5.vhd,../pcie0_examples/common/testbench/altpcie_pll_phy2.vhd,../pcie0_examples/common/testbench/altpcie_pll_phy3_62p5.vhd,../pcie0_examples/common/testbench/altpcie_pll_phy4_62p5.vhd,../pcie0_examples/common/testbench/altpcie_pll_phy5_62p5.vhd,../pcie0_examples/common/testbench/altpcietb_bfm_constants.vhd,../pcie0_examples/common/testbench/altpcietb_bfm_log.vhd,../pcie0_examples/common/testbench/altpcietb_bfm_common.vhd,../pcie0_examples/common/testbench/altpcietb_bfm_shmem.vhd,../pcie0_examples/common/testbench/altpcietb_bfm_req_intf.vhd,../pcie0_examples/common/testbench/altpcietb_bfm_rdwr.vhd,../pcie0_examples/common/testbench/altpcietb_bfm_configure.vhd,../pcie0_examples/sopc/testbench/altpcietb_bfm_driver.vhd,../pcie0_examples/sopc/testbench/pcie0_testbench.vhd,../pcie0_examples/common/testbench/altpcietb_bfm_vc_intf.vhd,../pcie0_examples/common/testbench/altpcietb_bfm_rp_top_x8_pipen1b.vhd,../pcie0_examples/common/testbench/altpcietb_bfm_rpvar_64b_x8_gen1_pipen1b.vho,../pcie0_examples/common/testbench/altpcietb_pipe_xtx2yrx.vhd,../pcie0_examples/common/testbench/altpcietb_pipe_phy.vhd,../pcie0_examples/common/testbench/altpcietb_rst_clk.vhd,../pcie0_examples/common/testbench/altpcietb_ltssm_mon.vhd";
      }
      class = "altera_avalon_pcie_compiler";
      class_version = "10.1";
      WIZARD_SCRIPT_ARGUMENTS 
      {
      }
      MASTER Rx_Interface
      {
         PORT_WIRING 
         {
            PORT AvlClk_i
            {
               type = "clk";
               width = "1";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT reset_n
            {
               type = "reset_n";
               width = "1";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT RxmIrqNum_i
            {
               type = "irqnumber";
               width = "6";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT RxmIrq_i
            {
               type = "irq";
               width = "1";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT RxmAddress_o
            {
               type = "address";
               width = "32";
               direction = "output";
               Is_Enabled = "1";
            }
            PORT RxmBurstCount_o
            {
               type = "burstcount";
               width = "10";
               direction = "output";
               Is_Enabled = "1";
            }
            PORT RxmByteEnable_o
            {
               type = "byteenable";
               width = "8";
               direction = "output";
               Is_Enabled = "1";
            }
            PORT RxmRead_o
            {
               type = "read";
               width = "1";
               direction = "output";
               Is_Enabled = "1";
            }
            PORT RxmReadData_i
            {
               type = "readdata";
               width = "64";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT RxmReadDataValid_i
            {
               type = "readdatavalid";
               width = "1";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT RxmWaitRequest_i
            {
               type = "waitrequest";
               width = "1";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT RxmWrite_o
            {
               type = "write";
               width = "1";
               direction = "output";
               Is_Enabled = "1";
            }
            PORT RxmWriteData_o
            {
               type = "writedata";
               width = "64";
               direction = "output";
               Is_Enabled = "1";
            }
            PORT RxmResetRequest_o
            {
               type = "resetrequest";
               width = "1";
               direction = "output";
               Is_Enabled = "1";
            }
         }
         SYSTEM_BUILDER_INFO 
         {
            Has_IRQ = "1";
            Irq_Scheme = "priority_encoded";
            Bus_Type = "avalon";
            Is_Asynchronous = "0";
            DBS_Big_Endian = "0";
            Adapts_To = "";
            Do_Stream_Reads = "0";
            Do_Stream_Writes = "0";
            Max_Address_Width = "32";
            Data_Width = "64";
            Address_Width = "32";
            Maximum_Burst_Size = "512";
            Register_Incoming_Signals = "0";
            Register_Outgoing_Signals = "0";
            Interleave_Bursts = "0";
            Linewrap_Bursts = "0";
            Burst_On_Burst_Boundaries_Only = "0";
            Always_Burst_Max_Burst = "0";
            Is_Big_Endian = "0";
            Is_Enabled = "1";
            Clock_Source = "pcie0_pcie_core_clk_out";
            Has_Clock = "1";
         }
         MEMORY_MAP 
         {
            Entry gpio_west/s1
            {
               address = "0x80004100";
               span = "0x00000020";
               is_bridge = "0";
            }
            Entry gpio_east/s1
            {
               address = "0x80004180";
               span = "0x00000020";
               is_bridge = "0";
            }
            Entry hsmc_misc_in/s1
            {
               address = "0x80004200";
               span = "0x00000020";
               is_bridge = "0";
            }
            Entry hsmc_misc_out/s1
            {
               address = "0x80004280";
               span = "0x00000020";
               is_bridge = "0";
            }
            Entry hsmc_misc_io/s1
            {
               address = "0x80004300";
               span = "0x00000020";
               is_bridge = "0";
            }
            Entry hsmc_bank2_west/s1
            {
               address = "0x80004380";
               span = "0x00000020";
               is_bridge = "0";
            }
            Entry hsmc_bank2_east/s1
            {
               address = "0x80004400";
               span = "0x00000020";
               is_bridge = "0";
            }
            Entry hsmc_bank3_west/s1
            {
               address = "0x80004480";
               span = "0x00000020";
               is_bridge = "0";
            }
            Entry hsmc_bank3_east/s1
            {
               address = "0x80004500";
               span = "0x00000020";
               is_bridge = "0";
            }
            Entry lpcpod_in/s1
            {
               address = "0x80004580";
               span = "0x00000020";
               is_bridge = "0";
            }
            Entry dma_0/control_port_slave
            {
               address = "0x80004000";
               is_bridge = "0";
               span = "0x00000040";
            }
            Entry pcie0/Control_Register_Access
            {
               address = "0x80000000";
               is_bridge = "0";
               span = "0x00004000";
            }
         }
      }
   }
   MODULE gpio_west
   {
      SLAVE s1
      {
         PORT_WIRING 
         {
            PORT clk
            {
               type = "clk";
               width = "1";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT reset_n
            {
               type = "reset_n";
               width = "1";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT address
            {
               type = "address";
               width = "2";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT write_n
            {
               type = "write_n";
               width = "1";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT writedata
            {
               type = "writedata";
               width = "17";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT chipselect
            {
               type = "chipselect";
               width = "1";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT readdata
            {
               type = "readdata";
               width = "17";
               direction = "output";
               Is_Enabled = "1";
            }
         }
         SYSTEM_BUILDER_INFO 
         {
            Bus_Type = "avalon";
            Write_Wait_States = "0cycles";
            Read_Wait_States = "1cycles";
            Hold_Time = "0cycles";
            Setup_Time = "0cycles";
            Is_Printable_Device = "0";
            Address_Alignment = "native";
            Well_Behaved_Waitrequest = "0";
            Is_Nonvolatile_Storage = "0";
            Read_Latency = "0";
            Is_Memory_Device = "0";
            Maximum_Pending_Read_Transactions = "0";
            Minimum_Uninterrupted_Run_Length = "1";
            Accepts_Internal_Connections = "1";
            Write_Latency = "0";
            Is_Flash = "0";
            Data_Width = "17";
            Address_Width = "2";
            Maximum_Burst_Size = "1";
            Register_Incoming_Signals = "0";
            Register_Outgoing_Signals = "0";
            Interleave_Bursts = "0";
            Linewrap_Bursts = "0";
            Burst_On_Burst_Boundaries_Only = "0";
            Always_Burst_Max_Burst = "0";
            Is_Big_Endian = "0";
            Is_Enabled = "1";
            MASTERED_BY pcie0/Rx_Interface
            {
               priority = "1";
               Offset_Address = "0x80004100";
            }
            Base_Address = "0x80004100";
            Has_IRQ = "0";
            Address_Group = "0";
            Is_Readable = "1";
            Is_Writable = "1";
            IRQ_MASTER pcie0/Rx_Interface
            {
               IRQ_Number = "NC";
            }
         }
      }
      PORT_WIRING 
      {
         PORT bidir_port
         {
            type = "export";
            width = "17";
            direction = "inout";
            Is_Enabled = "1";
            test_bench_value = "0";
         }
         PORT in_port
         {
            direction = "input";
            Is_Enabled = "0";
            width = "17";
         }
         PORT out_port
         {
            direction = "output";
            Is_Enabled = "0";
            width = "17";
         }
      }
      class = "altera_avalon_pio";
      class_version = "7.08101";
      SYSTEM_BUILDER_INFO 
      {
         Is_Enabled = "1";
         Instantiate_In_System_Module = "1";
         Wire_Test_Bench_Values = "1";
         Top_Level_Ports_Are_Enumerated = "1";
         Clock_Source = "pcie0_pcie_core_clk_out";
         Has_Clock = "1";
         Date_Modified = "";
         View 
         {
            MESSAGES 
            {
            }
            Settings_Summary = " 17-bit PIO using <br>
					 tri-state pins with edge type NONE and interrupt source NONE
					
					";
         }
      }
      WIZARD_SCRIPT_ARGUMENTS 
      {
         Do_Test_Bench_Wiring = "1";
         Driven_Sim_Value = "0";
         has_tri = "1";
         has_out = "0";
         has_in = "0";
         capture = "0";
         Data_Width = "17";
         reset_value = "0";
         edge_type = "NONE";
         irq_type = "NONE";
         bit_clearing_edge_register = "0";
         bit_modifying_output_register = "0";
      }
      HDL_INFO 
      {
         Precompiled_Simulation_Library_Files = "";
         Simulation_HDL_Files = "";
         Synthesis_HDL_Files = "__PROJECT_DIRECTORY__/gpio_west.vhd";
         Synthesis_Only_Files = "";
      }
   }
   MODULE gpio_east
   {
      SLAVE s1
      {
         PORT_WIRING 
         {
            PORT clk
            {
               type = "clk";
               width = "1";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT reset_n
            {
               type = "reset_n";
               width = "1";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT address
            {
               type = "address";
               width = "2";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT write_n
            {
               type = "write_n";
               width = "1";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT writedata
            {
               type = "writedata";
               width = "17";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT chipselect
            {
               type = "chipselect";
               width = "1";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT readdata
            {
               type = "readdata";
               width = "17";
               direction = "output";
               Is_Enabled = "1";
            }
         }
         SYSTEM_BUILDER_INFO 
         {
            Bus_Type = "avalon";
            Write_Wait_States = "0cycles";
            Read_Wait_States = "1cycles";
            Hold_Time = "0cycles";
            Setup_Time = "0cycles";
            Is_Printable_Device = "0";
            Address_Alignment = "native";
            Well_Behaved_Waitrequest = "0";
            Is_Nonvolatile_Storage = "0";
            Read_Latency = "0";
            Is_Memory_Device = "0";
            Maximum_Pending_Read_Transactions = "0";
            Minimum_Uninterrupted_Run_Length = "1";
            Accepts_Internal_Connections = "1";
            Write_Latency = "0";
            Is_Flash = "0";
            Data_Width = "17";
            Address_Width = "2";
            Maximum_Burst_Size = "1";
            Register_Incoming_Signals = "0";
            Register_Outgoing_Signals = "0";
            Interleave_Bursts = "0";
            Linewrap_Bursts = "0";
            Burst_On_Burst_Boundaries_Only = "0";
            Always_Burst_Max_Burst = "0";
            Is_Big_Endian = "0";
            Is_Enabled = "1";
            MASTERED_BY pcie0/Rx_Interface
            {
               priority = "1";
               Offset_Address = "0x80004180";
            }
            Base_Address = "0x80004180";
            Has_IRQ = "0";
            Address_Group = "0";
            Is_Readable = "1";
            Is_Writable = "1";
            IRQ_MASTER pcie0/Rx_Interface
            {
               IRQ_Number = "NC";
            }
         }
      }
      PORT_WIRING 
      {
         PORT bidir_port
         {
            type = "export";
            width = "17";
            direction = "inout";
            Is_Enabled = "1";
            test_bench_value = "0";
         }
         PORT in_port
         {
            direction = "input";
            Is_Enabled = "0";
            width = "17";
         }
         PORT out_port
         {
            direction = "output";
            Is_Enabled = "0";
            width = "17";
         }
      }
      class = "altera_avalon_pio";
      class_version = "7.08101";
      SYSTEM_BUILDER_INFO 
      {
         Is_Enabled = "1";
         Instantiate_In_System_Module = "1";
         Wire_Test_Bench_Values = "1";
         Top_Level_Ports_Are_Enumerated = "1";
         Clock_Source = "pcie0_pcie_core_clk_out";
         Has_Clock = "1";
         Date_Modified = "";
         View 
         {
            MESSAGES 
            {
            }
            Settings_Summary = " 17-bit PIO using <br>
					 tri-state pins with edge type NONE and interrupt source NONE
					
					";
         }
      }
      WIZARD_SCRIPT_ARGUMENTS 
      {
         Do_Test_Bench_Wiring = "1";
         Driven_Sim_Value = "0";
         has_tri = "1";
         has_out = "0";
         has_in = "0";
         capture = "0";
         Data_Width = "17";
         reset_value = "0";
         edge_type = "NONE";
         irq_type = "NONE";
         bit_clearing_edge_register = "0";
         bit_modifying_output_register = "0";
      }
      HDL_INFO 
      {
         Precompiled_Simulation_Library_Files = "";
         Simulation_HDL_Files = "";
         Synthesis_HDL_Files = "__PROJECT_DIRECTORY__/gpio_east.vhd";
         Synthesis_Only_Files = "";
      }
   }
   MODULE hsmc_misc_out
   {
      SLAVE s1
      {
         PORT_WIRING 
         {
            PORT clk
            {
               type = "clk";
               width = "1";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT reset_n
            {
               type = "reset_n";
               width = "1";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT address
            {
               type = "address";
               width = "2";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT write_n
            {
               type = "write_n";
               width = "1";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT writedata
            {
               type = "writedata";
               width = "5";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT chipselect
            {
               type = "chipselect";
               width = "1";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT readdata
            {
               type = "readdata";
               width = "5";
               direction = "output";
               Is_Enabled = "1";
            }
         }
         SYSTEM_BUILDER_INFO 
         {
            Bus_Type = "avalon";
            Write_Wait_States = "0cycles";
            Read_Wait_States = "1cycles";
            Hold_Time = "0cycles";
            Setup_Time = "0cycles";
            Is_Printable_Device = "0";
            Address_Alignment = "native";
            Well_Behaved_Waitrequest = "0";
            Is_Nonvolatile_Storage = "0";
            Read_Latency = "0";
            Is_Memory_Device = "0";
            Maximum_Pending_Read_Transactions = "0";
            Minimum_Uninterrupted_Run_Length = "1";
            Accepts_Internal_Connections = "1";
            Write_Latency = "0";
            Is_Flash = "0";
            Data_Width = "5";
            Address_Width = "2";
            Maximum_Burst_Size = "1";
            Register_Incoming_Signals = "0";
            Register_Outgoing_Signals = "0";
            Interleave_Bursts = "0";
            Linewrap_Bursts = "0";
            Burst_On_Burst_Boundaries_Only = "0";
            Always_Burst_Max_Burst = "0";
            Is_Big_Endian = "0";
            Is_Enabled = "1";
            MASTERED_BY pcie0/Rx_Interface
            {
               priority = "1";
               Offset_Address = "0x80004280";
            }
            Base_Address = "0x80004280";
            Has_IRQ = "0";
            Address_Group = "0";
            Is_Readable = "0";
            Is_Writable = "1";
            IRQ_MASTER pcie0/Rx_Interface
            {
               IRQ_Number = "NC";
            }
         }
      }
      PORT_WIRING 
      {
         PORT out_port
         {
            type = "export";
            width = "5";
            direction = "output";
            Is_Enabled = "1";
         }
         PORT in_port
         {
            direction = "input";
            Is_Enabled = "0";
            width = "5";
         }
         PORT bidir_port
         {
            direction = "inout";
            Is_Enabled = "0";
            width = "5";
         }
      }
      class = "altera_avalon_pio";
      class_version = "7.08101";
      SYSTEM_BUILDER_INFO 
      {
         Is_Enabled = "1";
         Instantiate_In_System_Module = "1";
         Wire_Test_Bench_Values = "1";
         Top_Level_Ports_Are_Enumerated = "1";
         Clock_Source = "pcie0_pcie_core_clk_out";
         Has_Clock = "1";
         Date_Modified = "";
         View 
         {
            MESSAGES 
            {
            }
            Settings_Summary = " 5-bit PIO using <br>
					
					
					 output pins";
         }
      }
      WIZARD_SCRIPT_ARGUMENTS 
      {
         Do_Test_Bench_Wiring = "0";
         Driven_Sim_Value = "0";
         has_tri = "0";
         has_out = "1";
         has_in = "0";
         capture = "0";
         Data_Width = "5";
         reset_value = "0";
         edge_type = "NONE";
         irq_type = "NONE";
         bit_clearing_edge_register = "0";
         bit_modifying_output_register = "0";
      }
      HDL_INFO 
      {
         Precompiled_Simulation_Library_Files = "";
         Simulation_HDL_Files = "";
         Synthesis_HDL_Files = "__PROJECT_DIRECTORY__/hsmc_misc_out.vhd";
         Synthesis_Only_Files = "";
      }
   }
   MODULE hsmc_misc_in
   {
      SLAVE s1
      {
         PORT_WIRING 
         {
            PORT clk
            {
               type = "clk";
               width = "1";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT reset_n
            {
               type = "reset_n";
               width = "1";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT address
            {
               type = "address";
               width = "2";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT readdata
            {
               type = "readdata";
               width = "5";
               direction = "output";
               Is_Enabled = "1";
            }
         }
         SYSTEM_BUILDER_INFO 
         {
            Bus_Type = "avalon";
            Write_Wait_States = "0cycles";
            Read_Wait_States = "1cycles";
            Hold_Time = "0cycles";
            Setup_Time = "0cycles";
            Is_Printable_Device = "0";
            Address_Alignment = "native";
            Well_Behaved_Waitrequest = "0";
            Is_Nonvolatile_Storage = "0";
            Read_Latency = "0";
            Is_Memory_Device = "0";
            Maximum_Pending_Read_Transactions = "0";
            Minimum_Uninterrupted_Run_Length = "1";
            Accepts_Internal_Connections = "1";
            Write_Latency = "0";
            Is_Flash = "0";
            Data_Width = "5";
            Address_Width = "2";
            Maximum_Burst_Size = "1";
            Register_Incoming_Signals = "0";
            Register_Outgoing_Signals = "0";
            Interleave_Bursts = "0";
            Linewrap_Bursts = "0";
            Burst_On_Burst_Boundaries_Only = "0";
            Always_Burst_Max_Burst = "0";
            Is_Big_Endian = "0";
            Is_Enabled = "1";
            MASTERED_BY pcie0/Rx_Interface
            {
               priority = "1";
               Offset_Address = "0x80004200";
            }
            Base_Address = "0x80004200";
            Has_IRQ = "0";
            Address_Group = "0";
            Is_Readable = "1";
            Is_Writable = "0";
            IRQ_MASTER pcie0/Rx_Interface
            {
               IRQ_Number = "NC";
            }
         }
      }
      PORT_WIRING 
      {
         PORT in_port
         {
            type = "export";
            width = "5";
            direction = "input";
            Is_Enabled = "1";
            test_bench_value = "0";
         }
         PORT out_port
         {
            direction = "output";
            Is_Enabled = "0";
            width = "5";
         }
         PORT bidir_port
         {
            direction = "inout";
            Is_Enabled = "0";
            width = "5";
         }
      }
      class = "altera_avalon_pio";
      class_version = "7.08101";
      SYSTEM_BUILDER_INFO 
      {
         Is_Enabled = "1";
         Instantiate_In_System_Module = "1";
         Wire_Test_Bench_Values = "1";
         Top_Level_Ports_Are_Enumerated = "1";
         Clock_Source = "pcie0_pcie_core_clk_out";
         Has_Clock = "1";
         Date_Modified = "";
         View 
         {
            MESSAGES 
            {
            }
            Settings_Summary = " 5-bit PIO using <br>
					
					 input pins with edge type NONE and interrupt source NONE
					";
         }
      }
      WIZARD_SCRIPT_ARGUMENTS 
      {
         Do_Test_Bench_Wiring = "1";
         Driven_Sim_Value = "0";
         has_tri = "0";
         has_out = "0";
         has_in = "1";
         capture = "0";
         Data_Width = "5";
         reset_value = "0";
         edge_type = "NONE";
         irq_type = "NONE";
         bit_clearing_edge_register = "0";
         bit_modifying_output_register = "0";
      }
      HDL_INFO 
      {
         Precompiled_Simulation_Library_Files = "";
         Simulation_HDL_Files = "";
         Synthesis_HDL_Files = "__PROJECT_DIRECTORY__/hsmc_misc_in.vhd";
         Synthesis_Only_Files = "";
      }
   }
   MODULE hsmc_bank2_west
   {
      SLAVE s1
      {
         PORT_WIRING 
         {
            PORT clk
            {
               type = "clk";
               width = "1";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT reset_n
            {
               type = "reset_n";
               width = "1";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT address
            {
               type = "address";
               width = "2";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT write_n
            {
               type = "write_n";
               width = "1";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT writedata
            {
               type = "writedata";
               width = "18";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT chipselect
            {
               type = "chipselect";
               width = "1";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT readdata
            {
               type = "readdata";
               width = "18";
               direction = "output";
               Is_Enabled = "1";
            }
         }
         SYSTEM_BUILDER_INFO 
         {
            Bus_Type = "avalon";
            Write_Wait_States = "0cycles";
            Read_Wait_States = "1cycles";
            Hold_Time = "0cycles";
            Setup_Time = "0cycles";
            Is_Printable_Device = "0";
            Address_Alignment = "native";
            Well_Behaved_Waitrequest = "0";
            Is_Nonvolatile_Storage = "0";
            Read_Latency = "0";
            Is_Memory_Device = "0";
            Maximum_Pending_Read_Transactions = "0";
            Minimum_Uninterrupted_Run_Length = "1";
            Accepts_Internal_Connections = "1";
            Write_Latency = "0";
            Is_Flash = "0";
            Data_Width = "18";
            Address_Width = "2";
            Maximum_Burst_Size = "1";
            Register_Incoming_Signals = "0";
            Register_Outgoing_Signals = "0";
            Interleave_Bursts = "0";
            Linewrap_Bursts = "0";
            Burst_On_Burst_Boundaries_Only = "0";
            Always_Burst_Max_Burst = "0";
            Is_Big_Endian = "0";
            Is_Enabled = "1";
            MASTERED_BY pcie0/Rx_Interface
            {
               priority = "1";
               Offset_Address = "0x80004380";
            }
            Base_Address = "0x80004380";
            Has_IRQ = "0";
            Address_Group = "0";
            Is_Readable = "1";
            Is_Writable = "1";
            IRQ_MASTER pcie0/Rx_Interface
            {
               IRQ_Number = "NC";
            }
         }
      }
      PORT_WIRING 
      {
         PORT bidir_port
         {
            type = "export";
            width = "18";
            direction = "inout";
            Is_Enabled = "1";
            test_bench_value = "0";
         }
         PORT in_port
         {
            direction = "input";
            Is_Enabled = "0";
            width = "18";
         }
         PORT out_port
         {
            direction = "output";
            Is_Enabled = "0";
            width = "18";
         }
      }
      class = "altera_avalon_pio";
      class_version = "7.08101";
      SYSTEM_BUILDER_INFO 
      {
         Is_Enabled = "1";
         Instantiate_In_System_Module = "1";
         Wire_Test_Bench_Values = "1";
         Top_Level_Ports_Are_Enumerated = "1";
         Clock_Source = "pcie0_pcie_core_clk_out";
         Has_Clock = "1";
         Date_Modified = "";
         View 
         {
            MESSAGES 
            {
            }
            Settings_Summary = " 18-bit PIO using <br>
					 tri-state pins with edge type NONE and interrupt source NONE
					
					";
         }
      }
      WIZARD_SCRIPT_ARGUMENTS 
      {
         Do_Test_Bench_Wiring = "1";
         Driven_Sim_Value = "0";
         has_tri = "1";
         has_out = "0";
         has_in = "0";
         capture = "0";
         Data_Width = "18";
         reset_value = "0";
         edge_type = "NONE";
         irq_type = "NONE";
         bit_clearing_edge_register = "0";
         bit_modifying_output_register = "0";
      }
      HDL_INFO 
      {
         Precompiled_Simulation_Library_Files = "";
         Simulation_HDL_Files = "";
         Synthesis_HDL_Files = "__PROJECT_DIRECTORY__/hsmc_bank2_west.vhd";
         Synthesis_Only_Files = "";
      }
   }
   MODULE hsmc_bank2_east
   {
      SLAVE s1
      {
         PORT_WIRING 
         {
            PORT clk
            {
               type = "clk";
               width = "1";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT reset_n
            {
               type = "reset_n";
               width = "1";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT address
            {
               type = "address";
               width = "2";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT write_n
            {
               type = "write_n";
               width = "1";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT writedata
            {
               type = "writedata";
               width = "18";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT chipselect
            {
               type = "chipselect";
               width = "1";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT readdata
            {
               type = "readdata";
               width = "18";
               direction = "output";
               Is_Enabled = "1";
            }
         }
         SYSTEM_BUILDER_INFO 
         {
            Bus_Type = "avalon";
            Write_Wait_States = "0cycles";
            Read_Wait_States = "1cycles";
            Hold_Time = "0cycles";
            Setup_Time = "0cycles";
            Is_Printable_Device = "0";
            Address_Alignment = "native";
            Well_Behaved_Waitrequest = "0";
            Is_Nonvolatile_Storage = "0";
            Read_Latency = "0";
            Is_Memory_Device = "0";
            Maximum_Pending_Read_Transactions = "0";
            Minimum_Uninterrupted_Run_Length = "1";
            Accepts_Internal_Connections = "1";
            Write_Latency = "0";
            Is_Flash = "0";
            Data_Width = "18";
            Address_Width = "2";
            Maximum_Burst_Size = "1";
            Register_Incoming_Signals = "0";
            Register_Outgoing_Signals = "0";
            Interleave_Bursts = "0";
            Linewrap_Bursts = "0";
            Burst_On_Burst_Boundaries_Only = "0";
            Always_Burst_Max_Burst = "0";
            Is_Big_Endian = "0";
            Is_Enabled = "1";
            MASTERED_BY pcie0/Rx_Interface
            {
               priority = "1";
               Offset_Address = "0x80004400";
            }
            Base_Address = "0x80004400";
            Has_IRQ = "0";
            Address_Group = "0";
            Is_Readable = "1";
            Is_Writable = "1";
            IRQ_MASTER pcie0/Rx_Interface
            {
               IRQ_Number = "NC";
            }
         }
      }
      PORT_WIRING 
      {
         PORT bidir_port
         {
            type = "export";
            width = "18";
            direction = "inout";
            Is_Enabled = "1";
            test_bench_value = "0";
         }
         PORT in_port
         {
            direction = "input";
            Is_Enabled = "0";
            width = "18";
         }
         PORT out_port
         {
            direction = "output";
            Is_Enabled = "0";
            width = "18";
         }
      }
      class = "altera_avalon_pio";
      class_version = "7.08101";
      SYSTEM_BUILDER_INFO 
      {
         Is_Enabled = "1";
         Instantiate_In_System_Module = "1";
         Wire_Test_Bench_Values = "1";
         Top_Level_Ports_Are_Enumerated = "1";
         Clock_Source = "pcie0_pcie_core_clk_out";
         Has_Clock = "1";
         Date_Modified = "";
         View 
         {
            MESSAGES 
            {
            }
            Settings_Summary = " 18-bit PIO using <br>
					 tri-state pins with edge type NONE and interrupt source NONE
					
					";
         }
      }
      WIZARD_SCRIPT_ARGUMENTS 
      {
         Do_Test_Bench_Wiring = "1";
         Driven_Sim_Value = "0";
         has_tri = "1";
         has_out = "0";
         has_in = "0";
         capture = "0";
         Data_Width = "18";
         reset_value = "0";
         edge_type = "NONE";
         irq_type = "NONE";
         bit_clearing_edge_register = "0";
         bit_modifying_output_register = "0";
      }
      HDL_INFO 
      {
         Precompiled_Simulation_Library_Files = "";
         Simulation_HDL_Files = "";
         Synthesis_HDL_Files = "__PROJECT_DIRECTORY__/hsmc_bank2_east.vhd";
         Synthesis_Only_Files = "";
      }
   }
   MODULE hsmc_bank3_west
   {
      SLAVE s1
      {
         PORT_WIRING 
         {
            PORT clk
            {
               type = "clk";
               width = "1";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT reset_n
            {
               type = "reset_n";
               width = "1";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT address
            {
               type = "address";
               width = "2";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT write_n
            {
               type = "write_n";
               width = "1";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT writedata
            {
               type = "writedata";
               width = "18";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT chipselect
            {
               type = "chipselect";
               width = "1";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT readdata
            {
               type = "readdata";
               width = "18";
               direction = "output";
               Is_Enabled = "1";
            }
         }
         SYSTEM_BUILDER_INFO 
         {
            Bus_Type = "avalon";
            Write_Wait_States = "0cycles";
            Read_Wait_States = "1cycles";
            Hold_Time = "0cycles";
            Setup_Time = "0cycles";
            Is_Printable_Device = "0";
            Address_Alignment = "native";
            Well_Behaved_Waitrequest = "0";
            Is_Nonvolatile_Storage = "0";
            Read_Latency = "0";
            Is_Memory_Device = "0";
            Maximum_Pending_Read_Transactions = "0";
            Minimum_Uninterrupted_Run_Length = "1";
            Accepts_Internal_Connections = "1";
            Write_Latency = "0";
            Is_Flash = "0";
            Data_Width = "18";
            Address_Width = "2";
            Maximum_Burst_Size = "1";
            Register_Incoming_Signals = "0";
            Register_Outgoing_Signals = "0";
            Interleave_Bursts = "0";
            Linewrap_Bursts = "0";
            Burst_On_Burst_Boundaries_Only = "0";
            Always_Burst_Max_Burst = "0";
            Is_Big_Endian = "0";
            Is_Enabled = "1";
            MASTERED_BY pcie0/Rx_Interface
            {
               priority = "1";
               Offset_Address = "0x80004480";
            }
            Base_Address = "0x80004480";
            Has_IRQ = "0";
            Address_Group = "0";
            Is_Readable = "1";
            Is_Writable = "1";
            IRQ_MASTER pcie0/Rx_Interface
            {
               IRQ_Number = "NC";
            }
         }
      }
      PORT_WIRING 
      {
         PORT bidir_port
         {
            type = "export";
            width = "18";
            direction = "inout";
            Is_Enabled = "1";
            test_bench_value = "0";
         }
         PORT in_port
         {
            direction = "input";
            Is_Enabled = "0";
            width = "18";
         }
         PORT out_port
         {
            direction = "output";
            Is_Enabled = "0";
            width = "18";
         }
      }
      class = "altera_avalon_pio";
      class_version = "7.08101";
      SYSTEM_BUILDER_INFO 
      {
         Is_Enabled = "1";
         Instantiate_In_System_Module = "1";
         Wire_Test_Bench_Values = "1";
         Top_Level_Ports_Are_Enumerated = "1";
         Clock_Source = "pcie0_pcie_core_clk_out";
         Has_Clock = "1";
         Date_Modified = "";
         View 
         {
            MESSAGES 
            {
            }
            Settings_Summary = " 18-bit PIO using <br>
					 tri-state pins with edge type NONE and interrupt source NONE
					
					";
         }
      }
      WIZARD_SCRIPT_ARGUMENTS 
      {
         Do_Test_Bench_Wiring = "1";
         Driven_Sim_Value = "0";
         has_tri = "1";
         has_out = "0";
         has_in = "0";
         capture = "0";
         Data_Width = "18";
         reset_value = "0";
         edge_type = "NONE";
         irq_type = "NONE";
         bit_clearing_edge_register = "0";
         bit_modifying_output_register = "0";
      }
      HDL_INFO 
      {
         Precompiled_Simulation_Library_Files = "";
         Simulation_HDL_Files = "";
         Synthesis_HDL_Files = "__PROJECT_DIRECTORY__/hsmc_bank3_west.vhd";
         Synthesis_Only_Files = "";
      }
   }
   MODULE hsmc_bank3_east
   {
      SLAVE s1
      {
         PORT_WIRING 
         {
            PORT clk
            {
               type = "clk";
               width = "1";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT reset_n
            {
               type = "reset_n";
               width = "1";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT address
            {
               type = "address";
               width = "2";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT write_n
            {
               type = "write_n";
               width = "1";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT writedata
            {
               type = "writedata";
               width = "18";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT chipselect
            {
               type = "chipselect";
               width = "1";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT readdata
            {
               type = "readdata";
               width = "18";
               direction = "output";
               Is_Enabled = "1";
            }
         }
         SYSTEM_BUILDER_INFO 
         {
            Bus_Type = "avalon";
            Write_Wait_States = "0cycles";
            Read_Wait_States = "1cycles";
            Hold_Time = "0cycles";
            Setup_Time = "0cycles";
            Is_Printable_Device = "0";
            Address_Alignment = "native";
            Well_Behaved_Waitrequest = "0";
            Is_Nonvolatile_Storage = "0";
            Read_Latency = "0";
            Is_Memory_Device = "0";
            Maximum_Pending_Read_Transactions = "0";
            Minimum_Uninterrupted_Run_Length = "1";
            Accepts_Internal_Connections = "1";
            Write_Latency = "0";
            Is_Flash = "0";
            Data_Width = "18";
            Address_Width = "2";
            Maximum_Burst_Size = "1";
            Register_Incoming_Signals = "0";
            Register_Outgoing_Signals = "0";
            Interleave_Bursts = "0";
            Linewrap_Bursts = "0";
            Burst_On_Burst_Boundaries_Only = "0";
            Always_Burst_Max_Burst = "0";
            Is_Big_Endian = "0";
            Is_Enabled = "1";
            MASTERED_BY pcie0/Rx_Interface
            {
               priority = "1";
               Offset_Address = "0x80004500";
            }
            Base_Address = "0x80004500";
            Has_IRQ = "0";
            Address_Group = "0";
            Is_Readable = "1";
            Is_Writable = "1";
            IRQ_MASTER pcie0/Rx_Interface
            {
               IRQ_Number = "NC";
            }
         }
      }
      PORT_WIRING 
      {
         PORT bidir_port
         {
            type = "export";
            width = "18";
            direction = "inout";
            Is_Enabled = "1";
            test_bench_value = "0";
         }
         PORT in_port
         {
            direction = "input";
            Is_Enabled = "0";
            width = "18";
         }
         PORT out_port
         {
            direction = "output";
            Is_Enabled = "0";
            width = "18";
         }
      }
      class = "altera_avalon_pio";
      class_version = "7.08101";
      SYSTEM_BUILDER_INFO 
      {
         Is_Enabled = "1";
         Instantiate_In_System_Module = "1";
         Wire_Test_Bench_Values = "1";
         Top_Level_Ports_Are_Enumerated = "1";
         Clock_Source = "pcie0_pcie_core_clk_out";
         Has_Clock = "1";
         Date_Modified = "";
         View 
         {
            MESSAGES 
            {
            }
            Settings_Summary = " 18-bit PIO using <br>
					 tri-state pins with edge type NONE and interrupt source NONE
					
					";
         }
      }
      WIZARD_SCRIPT_ARGUMENTS 
      {
         Do_Test_Bench_Wiring = "1";
         Driven_Sim_Value = "0";
         has_tri = "1";
         has_out = "0";
         has_in = "0";
         capture = "0";
         Data_Width = "18";
         reset_value = "0";
         edge_type = "NONE";
         irq_type = "NONE";
         bit_clearing_edge_register = "0";
         bit_modifying_output_register = "0";
      }
      HDL_INFO 
      {
         Precompiled_Simulation_Library_Files = "";
         Simulation_HDL_Files = "";
         Synthesis_HDL_Files = "__PROJECT_DIRECTORY__/hsmc_bank3_east.vhd";
         Synthesis_Only_Files = "";
      }
   }
   MODULE lpcpod_in
   {
      SLAVE s1
      {
         PORT_WIRING 
         {
            PORT clk
            {
               type = "clk";
               width = "1";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT reset_n
            {
               type = "reset_n";
               width = "1";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT address
            {
               type = "address";
               width = "2";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT readdata
            {
               type = "readdata";
               width = "8";
               direction = "output";
               Is_Enabled = "1";
            }
         }
         SYSTEM_BUILDER_INFO 
         {
            Bus_Type = "avalon";
            Write_Wait_States = "0cycles";
            Read_Wait_States = "1cycles";
            Hold_Time = "0cycles";
            Setup_Time = "0cycles";
            Is_Printable_Device = "0";
            Address_Alignment = "native";
            Well_Behaved_Waitrequest = "0";
            Is_Nonvolatile_Storage = "0";
            Read_Latency = "0";
            Is_Memory_Device = "0";
            Maximum_Pending_Read_Transactions = "0";
            Minimum_Uninterrupted_Run_Length = "1";
            Accepts_Internal_Connections = "1";
            Write_Latency = "0";
            Is_Flash = "0";
            Data_Width = "8";
            Address_Width = "2";
            Maximum_Burst_Size = "1";
            Register_Incoming_Signals = "0";
            Register_Outgoing_Signals = "0";
            Interleave_Bursts = "0";
            Linewrap_Bursts = "0";
            Burst_On_Burst_Boundaries_Only = "0";
            Always_Burst_Max_Burst = "0";
            Is_Big_Endian = "0";
            Is_Enabled = "1";
            MASTERED_BY pcie0/Rx_Interface
            {
               priority = "1";
               Offset_Address = "0x80004580";
            }
            Base_Address = "0x80004580";
            Has_IRQ = "0";
            Address_Group = "0";
            Is_Readable = "1";
            Is_Writable = "0";
            IRQ_MASTER pcie0/Rx_Interface
            {
               IRQ_Number = "NC";
            }
         }
      }
      PORT_WIRING 
      {
         PORT in_port
         {
            type = "export";
            width = "8";
            direction = "input";
            Is_Enabled = "1";
            test_bench_value = "0";
         }
         PORT out_port
         {
            direction = "output";
            Is_Enabled = "0";
            width = "8";
         }
         PORT bidir_port
         {
            direction = "inout";
            Is_Enabled = "0";
            width = "8";
         }
      }
      class = "altera_avalon_pio";
      class_version = "7.08101";
      SYSTEM_BUILDER_INFO 
      {
         Is_Enabled = "1";
         Instantiate_In_System_Module = "1";
         Wire_Test_Bench_Values = "1";
         Top_Level_Ports_Are_Enumerated = "1";
         Clock_Source = "pcie0_pcie_core_clk_out";
         Has_Clock = "1";
         Date_Modified = "";
         View 
         {
            MESSAGES 
            {
            }
            Settings_Summary = " 8-bit PIO using <br>
					
					 input pins with edge type NONE and interrupt source NONE
					";
         }
      }
      WIZARD_SCRIPT_ARGUMENTS 
      {
         Do_Test_Bench_Wiring = "1";
         Driven_Sim_Value = "0";
         has_tri = "0";
         has_out = "0";
         has_in = "1";
         capture = "0";
         Data_Width = "8";
         reset_value = "0";
         edge_type = "NONE";
         irq_type = "NONE";
         bit_clearing_edge_register = "0";
         bit_modifying_output_register = "0";
      }
      HDL_INFO 
      {
         Precompiled_Simulation_Library_Files = "";
         Simulation_HDL_Files = "";
         Synthesis_HDL_Files = "__PROJECT_DIRECTORY__/lpcpod_in.vhd";
         Synthesis_Only_Files = "";
      }
   }
   MODULE hsmc_misc_io
   {
      SLAVE s1
      {
         PORT_WIRING 
         {
            PORT clk
            {
               type = "clk";
               width = "1";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT reset_n
            {
               type = "reset_n";
               width = "1";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT address
            {
               type = "address";
               width = "2";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT write_n
            {
               type = "write_n";
               width = "1";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT writedata
            {
               type = "writedata";
               width = "2";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT chipselect
            {
               type = "chipselect";
               width = "1";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT readdata
            {
               type = "readdata";
               width = "2";
               direction = "output";
               Is_Enabled = "1";
            }
         }
         SYSTEM_BUILDER_INFO 
         {
            Bus_Type = "avalon";
            Write_Wait_States = "0cycles";
            Read_Wait_States = "1cycles";
            Hold_Time = "0cycles";
            Setup_Time = "0cycles";
            Is_Printable_Device = "0";
            Address_Alignment = "native";
            Well_Behaved_Waitrequest = "0";
            Is_Nonvolatile_Storage = "0";
            Read_Latency = "0";
            Is_Memory_Device = "0";
            Maximum_Pending_Read_Transactions = "0";
            Minimum_Uninterrupted_Run_Length = "1";
            Accepts_Internal_Connections = "1";
            Write_Latency = "0";
            Is_Flash = "0";
            Data_Width = "2";
            Address_Width = "2";
            Maximum_Burst_Size = "1";
            Register_Incoming_Signals = "0";
            Register_Outgoing_Signals = "0";
            Interleave_Bursts = "0";
            Linewrap_Bursts = "0";
            Burst_On_Burst_Boundaries_Only = "0";
            Always_Burst_Max_Burst = "0";
            Is_Big_Endian = "0";
            Is_Enabled = "1";
            MASTERED_BY pcie0/Rx_Interface
            {
               priority = "1";
               Offset_Address = "0x80004300";
            }
            Base_Address = "0x80004300";
            Has_IRQ = "0";
            Address_Group = "0";
            Is_Readable = "1";
            Is_Writable = "1";
            IRQ_MASTER pcie0/Rx_Interface
            {
               IRQ_Number = "NC";
            }
         }
      }
      PORT_WIRING 
      {
         PORT bidir_port
         {
            type = "export";
            width = "2";
            direction = "inout";
            Is_Enabled = "1";
            test_bench_value = "0";
         }
         PORT in_port
         {
            direction = "input";
            Is_Enabled = "0";
            width = "2";
         }
         PORT out_port
         {
            direction = "output";
            Is_Enabled = "0";
            width = "2";
         }
      }
      class = "altera_avalon_pio";
      class_version = "7.08101";
      SYSTEM_BUILDER_INFO 
      {
         Is_Enabled = "1";
         Instantiate_In_System_Module = "1";
         Wire_Test_Bench_Values = "1";
         Top_Level_Ports_Are_Enumerated = "1";
         Clock_Source = "pcie0_pcie_core_clk_out";
         Has_Clock = "1";
         Date_Modified = "";
         View 
         {
            MESSAGES 
            {
            }
            Settings_Summary = " 2-bit PIO using <br>
					 tri-state pins with edge type NONE and interrupt source NONE
					
					";
         }
      }
      WIZARD_SCRIPT_ARGUMENTS 
      {
         Do_Test_Bench_Wiring = "1";
         Driven_Sim_Value = "0";
         has_tri = "1";
         has_out = "0";
         has_in = "0";
         capture = "0";
         Data_Width = "2";
         reset_value = "0";
         edge_type = "NONE";
         irq_type = "NONE";
         bit_clearing_edge_register = "0";
         bit_modifying_output_register = "0";
      }
      HDL_INFO 
      {
         Precompiled_Simulation_Library_Files = "";
         Simulation_HDL_Files = "";
         Synthesis_HDL_Files = "__PROJECT_DIRECTORY__/hsmc_misc_io.vhd";
         Synthesis_Only_Files = "";
      }
   }
   MODULE dma_0
   {
      SLAVE control_port_slave
      {
         PORT_WIRING 
         {
            PORT clk
            {
               type = "clk";
               width = "1";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT system_reset_n
            {
               type = "reset_n";
               width = "1";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT dma_ctl_irq
            {
               type = "irq";
               width = "1";
               direction = "output";
               Is_Enabled = "1";
            }
            PORT dma_ctl_address
            {
               type = "address";
               width = "3";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT dma_ctl_chipselect
            {
               type = "chipselect";
               width = "1";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT dma_ctl_readdata
            {
               type = "readdata";
               width = "21";
               direction = "output";
               Is_Enabled = "1";
            }
            PORT dma_ctl_readyfordata
            {
               type = "readyfordata";
               width = "1";
               direction = "output";
               Is_Enabled = "1";
            }
            PORT dma_ctl_write_n
            {
               type = "write_n";
               width = "1";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT dma_ctl_writedata
            {
               type = "writedata";
               width = "21";
               direction = "input";
               Is_Enabled = "1";
            }
         }
         SYSTEM_BUILDER_INFO 
         {
            Has_IRQ = "1";
            Bus_Type = "avalon";
            Write_Wait_States = "1cycles";
            Read_Wait_States = "1cycles";
            Hold_Time = "0cycles";
            Setup_Time = "0cycles";
            Is_Printable_Device = "0";
            Address_Alignment = "native";
            Well_Behaved_Waitrequest = "0";
            Is_Nonvolatile_Storage = "0";
            Read_Latency = "0";
            Is_Memory_Device = "0";
            Maximum_Pending_Read_Transactions = "0";
            Minimum_Uninterrupted_Run_Length = "1";
            Accepts_Internal_Connections = "1";
            Write_Latency = "0";
            Is_Flash = "0";
            Data_Width = "21";
            Address_Width = "3";
            Maximum_Burst_Size = "1";
            Register_Incoming_Signals = "0";
            Register_Outgoing_Signals = "0";
            Interleave_Bursts = "0";
            Linewrap_Bursts = "0";
            Burst_On_Burst_Boundaries_Only = "0";
            Always_Burst_Max_Burst = "0";
            Is_Big_Endian = "0";
            Is_Enabled = "1";
            MASTERED_BY pcie0/Rx_Interface
            {
               priority = "1";
               Offset_Address = "0x80004000";
            }
            Base_Address = "0x80004000";
            Address_Group = "0";
            IRQ_MASTER pcie0/Rx_Interface
            {
               IRQ_Number = "NC";
            }
         }
      }
      MASTER write_master
      {
         SYSTEM_BUILDER_INFO 
         {
            Bus_Type = "avalon";
            Is_Asynchronous = "0";
            DBS_Big_Endian = "0";
            Adapts_To = "";
            Do_Stream_Reads = "0";
            Do_Stream_Writes = "1";
            Max_Address_Width = "32";
            Data_Width = "64";
            Address_Width = "20";
            Maximum_Burst_Size = "1";
            Register_Incoming_Signals = "0";
            Register_Outgoing_Signals = "0";
            Interleave_Bursts = "0";
            Linewrap_Bursts = "0";
            Burst_On_Burst_Boundaries_Only = "0";
            Always_Burst_Max_Burst = "0";
            Is_Big_Endian = "0";
            Is_Enabled = "1";
            Is_Readable = "0";
            Is_Writable = "1";
         }
         PORT_WIRING 
         {
            PORT write_address
            {
               type = "address";
               width = "20";
               direction = "output";
               Is_Enabled = "1";
            }
            PORT write_byteenable
            {
               type = "byteenable";
               width = "8";
               direction = "output";
               Is_Enabled = "1";
            }
            PORT write_chipselect
            {
               type = "chipselect";
               width = "1";
               direction = "output";
               Is_Enabled = "1";
            }
            PORT write_endofpacket
            {
               type = "endofpacket";
               width = "1";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT write_waitrequest
            {
               type = "waitrequest";
               width = "1";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT write_write_n
            {
               type = "write_n";
               width = "1";
               direction = "output";
               Is_Enabled = "1";
            }
            PORT write_writedata
            {
               type = "writedata";
               width = "64";
               direction = "output";
               Is_Enabled = "1";
            }
         }
         MEMORY_MAP 
         {
            Entry pcie0/Tx_Interface
            {
               address = "0x00000000";
               span = "0x00100000";
               is_bridge = "0";
            }
         }
      }
      MASTER read_master
      {
         SYSTEM_BUILDER_INFO 
         {
            Bus_Type = "avalon";
            Is_Asynchronous = "0";
            DBS_Big_Endian = "0";
            Adapts_To = "";
            Do_Stream_Reads = "1";
            Do_Stream_Writes = "0";
            Max_Address_Width = "32";
            Data_Width = "64";
            Address_Width = "20";
            Maximum_Burst_Size = "1";
            Register_Incoming_Signals = "0";
            Register_Outgoing_Signals = "0";
            Interleave_Bursts = "0";
            Linewrap_Bursts = "0";
            Burst_On_Burst_Boundaries_Only = "0";
            Always_Burst_Max_Burst = "0";
            Is_Big_Endian = "0";
            Is_Enabled = "1";
            Is_Readable = "1";
            Is_Writable = "0";
         }
         PORT_WIRING 
         {
            PORT read_address
            {
               type = "address";
               width = "20";
               direction = "output";
               Is_Enabled = "1";
            }
            PORT read_chipselect
            {
               type = "chipselect";
               width = "1";
               direction = "output";
               Is_Enabled = "1";
            }
            PORT read_endofpacket
            {
               type = "endofpacket";
               width = "1";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT read_flush
            {
               type = "flush";
               width = "1";
               direction = "output";
               Is_Enabled = "1";
            }
            PORT read_read_n
            {
               type = "read_n";
               width = "1";
               direction = "output";
               Is_Enabled = "1";
            }
            PORT read_readdata
            {
               type = "readdata";
               width = "64";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT read_readdatavalid
            {
               type = "readdatavalid";
               width = "1";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT read_waitrequest
            {
               type = "waitrequest";
               width = "1";
               direction = "input";
               Is_Enabled = "1";
            }
         }
         MEMORY_MAP 
         {
            Entry pcie0/Tx_Interface
            {
               address = "0x00000000";
               span = "0x00100000";
               is_bridge = "0";
            }
         }
      }
      WIZARD_SCRIPT_ARGUMENTS 
      {
         readaddress_reset_value = "0x000";
         writeaddress_reset_value = "0x000";
         length_reset_value = "0x000";
         control_byte_reset_value = "0";
         control_hw_reset_value = "0";
         control_word_reset_value = "1";
         control_doubleword_reset_value = "0";
         control_quadword_reset_value = "0";
         control_softwarereset_reset_value = "0";
         control_go_reset_value = "0";
         control_i_en_reset_value = "0";
         control_reen_reset_value = "0";
         control_ween_reset_value = "0";
         control_leen_reset_value = "1";
         control_rcon_reset_value = "0";
         control_wcon_reset_value = "0";
         lengthwidth = "13";
         burst_enable = "0";
         fifo_in_logic_elements = "0";
         allow_byte_transactions = "1";
         allow_hw_transactions = "1";
         allow_word_transactions = "1";
         allow_doubleword_transactions = "1";
         allow_quadword_transactions = "1";
         max_burst_size = "128";
         big_endian = "0";
         fifo_depth = "32";
         read_data_width = "64";
         write_data_width = "64";
         read_address_width = "20";
         write_address_width = "20";
         max_slave_address_span = "1048576";
         user_defined_fifo_depth = "1";
         control_byte_access_reset_value = "0";
         altera_show_unpublished_features = "0";
      }
      class = "altera_avalon_dma";
      class_version = "7.08101";
      SYSTEM_BUILDER_INFO 
      {
         Is_Enabled = "1";
         Clock_Source = "pcie0_pcie_core_clk_out";
         Has_Clock = "1";
         Instantiate_In_System_Module = "1";
         Top_Level_Ports_Are_Enumerated = "1";
         View 
         {
            MESSAGES 
            {
            }
         }
      }
      HDL_INFO 
      {
         Precompiled_Simulation_Library_Files = "";
         Simulation_HDL_Files = "";
         Synthesis_HDL_Files = "__PROJECT_DIRECTORY__/dma_0.vhd";
         Synthesis_Only_Files = "";
      }
      PORT_WIRING 
      {
      }
      SIMULATION 
      {
         DISPLAY 
         {
            SIGNAL aaa
            {
               format = "Logic";
               name = "busy";
               radix = "hexadecimal";
            }
            SIGNAL aab
            {
               format = "Logic";
               name = "done";
               radix = "hexadecimal";
            }
            SIGNAL aac
            {
               format = "Logic";
               name = "length";
               radix = "hexadecimal";
            }
            SIGNAL aad
            {
               format = "Logic";
               name = "fifo_empty";
               radix = "hexadecimal";
            }
            SIGNAL aae
            {
               format = "Logic";
               name = "p1_fifo_full";
               radix = "hexadecimal";
            }
            SIGNAL aaf
            {
               format = "Divider";
               name = "dma_0 read_master";
               radix = "";
            }
            SIGNAL aag
            {
               format = "Literal";
               name = "read_address";
               radix = "hexadecimal";
            }
            SIGNAL aah
            {
               format = "Logic";
               name = "read_chipselect";
               radix = "hexadecimal";
            }
            SIGNAL aai
            {
               format = "Logic";
               name = "read_endofpacket";
               radix = "hexadecimal";
            }
            SIGNAL aaj
            {
               format = "Logic";
               name = "read_flush";
               radix = "hexadecimal";
            }
            SIGNAL aak
            {
               format = "Logic";
               name = "read_read_n";
               radix = "hexadecimal";
            }
            SIGNAL aal
            {
               format = "Literal";
               name = "read_readdata";
               radix = "hexadecimal";
            }
            SIGNAL aam
            {
               format = "Logic";
               name = "read_readdatavalid";
               radix = "hexadecimal";
            }
            SIGNAL aan
            {
               format = "Logic";
               name = "read_waitrequest";
               radix = "hexadecimal";
            }
            SIGNAL aao
            {
               format = "Divider";
               name = "dma_0 write_master";
               radix = "";
            }
            SIGNAL aap
            {
               format = "Literal";
               name = "write_address";
               radix = "hexadecimal";
            }
            SIGNAL aaq
            {
               format = "Logic";
               name = "write_byteenable";
               radix = "hexadecimal";
            }
            SIGNAL aar
            {
               format = "Logic";
               name = "write_chipselect";
               radix = "hexadecimal";
            }
            SIGNAL aas
            {
               format = "Logic";
               name = "write_endofpacket";
               radix = "hexadecimal";
            }
            SIGNAL aat
            {
               format = "Logic";
               name = "write_waitrequest";
               radix = "hexadecimal";
            }
            SIGNAL aau
            {
               format = "Logic";
               name = "write_write_n";
               radix = "hexadecimal";
            }
            SIGNAL aav
            {
               format = "Literal";
               name = "write_writedata";
               radix = "hexadecimal";
            }
         }
      }
   }
}
